CY7C008/009 CY7C018/01964K/128K x 8/9 Dual-Port Static RAM
CY7C008/009 CY7C018/019
64K/128K x 8/9 Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow simultaneous access of the same memory location • 64K x 8 organization (CY7C008) • 128K x 8 organization (CY7C009) • 64K x 9 organization (CY7C018) • 128K x 9 organization (CY7C019) • 0.35-micron CMOS for optimum speed/power • High-speed access: 12[1]/15/20 ns • Low operating power — Active: ICC = 180 mA (typical) — Standby: ISB3 = 0.05 mA (typical) • Fully asynchronous operation • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flags for port-to-port communication • Dual Chip Enables • Pin select for Master or Slave • Commercial and Industrial temperature ranges • Available in 100-pin TQFP
Logic Block Diagram
R/WL CE0L CE1L OEL CEL CER R/WR CE0R CE1R OER
[2]
8/9
8/9
[2]
I/O0L–I/O7/8L I/O Control I/O Control
I/O0R–I/O7/8R
A0L–A15/16L
[3]
16/17
Address Decode
16/17
True Dual-Ported RAM Array
Address Decode
16/17
16/17
A0R–A15/16R
[3]
[3]
[3]
A0L–A15/16L CEL OEL R/WL SEML
[4]
Interrupt Semaphore Arbitration
A0R–A15/16R CER OER R/WR SEMR
[4]
BUSYL INTL M/S
Notes: 1. 2. 3. 4. See page 6 for Load Conditions. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. A0–A15 for 64K devices; A0–A16 for 128K. BUSY is an output in master mode and an input in slave mode.
BUSYR INTR
Cypress Semiconductor Corporation Document #: 38-06041 Rev. *C
•
3901 North First Street
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San Jose
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CA 95134 • 408-943-2600 Revised June 22, 2004
CY7C008/009 CY7C018/019
Functional Description
The CY7C008/009 and CY7C018/019 are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C008/009 and CY7C018/019 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.
Pin Configurations
100-Pin TQFP (Top View)
BUSYL BUSYR GND INTR INTL A0R A1R A2R A3R A4R A5R A6R M/S A6L A5L A4L A3L A2L A1L A0L NC NC NC NC NC 75 74 73 72 71 70 69 68 67 66 65
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L [5] A16L VCC NC NC NC NC CE0L CE1L SEML R/WL OEL GND NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R [5] GND NC NC NC NC CE0R CE1R SEMR R/WR OER GND GND NC
CY7C009 (128K x 8) CY7C008 (64K x 8)
64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/01R
GND
GND
GND
NC
VCC
VCC
NC
NC
Note: 5. This pin is NC for CY7C008.
Document #: 38-06041 Rev. *C
NC
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CY7C008/009 CY7C018/019
Pin Configurations (continued)
BUSYR
100-Pin TQFP (Top View)
BUSYL GND INTL GND VCC A1L M/S A6L A5L A4L A3L A2L A0L NC NC
INTR
A0R
A1R
A2R
A3R
A4R
A5R
A6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L [6] A16L VCC NC NC NC NC CE0L CE1L SEML R/WL OEL GND NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R [6] GND NC NC NC NC CE0R CE1R SEMR R/WR OER GND GND NC
CY7C019 (128K x 9) CY7C018 (64K x 9)
NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O1L
I/O0L
I/O2L
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/01R
GND
GND
GND
VCC
VCC
Selection Guide
CY7C008/009 CY7C018/019 -12[1] Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for ISB1 (mA) (Both ports TTL level) Typical Standby Current for ISB3 (mA) (Both ports CMOS level)
Note: 6. This pin is NC for CY7C018.
CY7C008/009 CY7C018/019 -15 15 190 50 0.05
NC
CY7C008/009 CY7C018/019 -20 20 180 45 0.05
12 195 55 0.05
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CY7C008/009 CY7C018/019
Pin Definitions
Left Port CE0L, CE1L R/WL OEL A0L–A16L I/O0L–I/O8L SEML INTL BUSYL M/S VCC GND NC Right Port CE0R, CE1R R/WR OER A0R–A16R I/O0R–I/O8R SEMR INTR BUSYR Description Chip Enable (CE is LOW when CE0 £ VIL and CE1 Š VIH) Read/Write Enable Output Enable Address (A0–A15 for 64K devices and A0–A16 for 128K devices) Data Bus Input/Output (I/O0–I/O7 for x8 devices and I/O0–I/O8 for x9) Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground No Connect Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >1100V Latch-Up Current.................................................... >200 mA
Maximum Ratings[7]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied.............................................–55°C to +125°C Supply Voltage to Ground Potential ............... –0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V DC Input Voltage[8]......................................... –0.5V to +7.0V
Operating Range
Range Commercial Industrial[9] Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10%
Notes: 7. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 8. Pulse width < 20 ns. 9. Industrial parts are available in CY7C009 and CY7C019 only.
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CY7C008/009 CY7C018/019
Electrical Characteristics Over the Operating Range
CY7C008/009 CY7C018/019 Parameter VOH VOL VIH VIL IOZ ICC -12[1] Description Output HIGH Voltage (VCC=Min., IOH= –4.0 mA) Output LOW Voltage (VCC=Min., IOH= +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC = Max., IOUT=0 mA) Outputs Disabled Standby Current (Both Ports TTL Level) CEL & CER ≥ VIH, f = fMAX Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL & CER ≥ VCC – 0.2V, f = 0 Com’l . Ind.[9] Com’l . Ind.[9] Com’l . Ind.[9] Com’l . Ind.[9] 115 185 110 160 0.05 0.5 0.05 0.5 125 205 120 180 55 75 50 70 –10 195 2.2 0.8 10 325 –10 190 Min. 2.4 0.4 2.2 0.8 10 280 –10 180 305 45 60 110 125 0.05 0.05 100 115 Typ. Max. Min. 2.4 0.4 2.2 0.8 10 265 290 65 80 160 175 0.5 0.5 140 155 -15 Typ. Max. Min. 2.4 0.4 -20 Typ. Max. Unit V V V V µA mA mA mA mA mA mA mA mA mA mA
ISB1
ISB2
ISB3
ISB4
Standby Current (One Port Com’l CMOS Level) . CEL | CER ≥ VIH, f = fMAX[10] Ind.[9]
.
Capacitance[11]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
Note: 10. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3
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CY7C008/009 CY7C018/019
AC Test Loads and Waveforms
5V 5V R1 = 893Ω OUTPUT C = 30 pF R2 = 347Ω VTH = 1.4V OUTPUT C = 30 pF RTH = 250Ω R1 = 893Ω OUTPUT C = 5 pF R2 = 347Ω
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, & tLZWE including scope and jig)
ALL INPUT PULSES
3.0V GND 10% ≤ 3 ns 90% 90% 10% ≤ 3 ns
AC Test Loads (Applicable to -12 only)[12]
1.00
∆ (ns) for all -12 access times
OUTPUT C
Z0 = 50Ω
R = 50Ω
0.90
0.80
0.70
VTH = 1.4V
0.60
0.50
(a) Load 1 (-12 only)
0.40
0.30
0.20
0.10
0.00 0 5 10 15 20 25 30
Capacitance (pF)
(b) Load Derating Curve
Notes: 11. Tested initially and after any design or process changes that may affect these parameters. 12. Test conditions: C = 0 pF.
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CY7C008/009 CY7C018/019
S w i t c h i n g C h a r a c t e r i s t i c s
Over the Operating Range[13] CY7C008/009 CY7C018/019 -12[1] Parameter READ CYCLE tRC tAA tOHA tACE[14] tDOE tLZOE[15, 16, 17] tHZOE[13, 16, 17] tLZCE[15, 16, 17] tHZCE[15, 16, 17] tPU[17] tPD[17] tABE[14]
