FTG

CY28349B FTG for Intel® Pentium® 4 CPU and Chipsets Features • Compatible to Intel® CK-Titan and CK-408 Clock • • • • • • Synthesizer/driver specifications System frequency synthesizer for Intel Brookdale 845 and Brookdale – G Pentium® 4 chipsets Programmable clock output frequency with less than 1-MHz increment Integrated fail-safe Watchdog timer for system recovery Automatically switch to hardware-selected or softwareprogrammed clock frequency when w timer time-out Fixed 3V66 and PCI output frequency mode. Capable of generating system RESET after a Watchdog timer time-out occurs or a change in output frequency via SMBus interface • Support SMBus byte read/write and block read/ write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable drive strength support • Programmable output skew support • Power management control inputs • Available in 48-pin SSOP CPU x3 3V66 x4 PCI x 10 REF x2 48M x1 24_48M x1 Block Diagram X1 X2 Pin Configuration [1] VDD_REF REF0:1 XTAL OSC PLL 1 PLL Ref Freq Divider Network *FS0:4 VTT_PWRGD# www.DataSheet4U.com *MULTSEL0:1 PWR_DWN# PLL2 2 SDATA SCLK SMBus Logic *MULTSEL1/REF1 VDD_REF X1 X2 GND_PCI *FS2/PCI_F0 *FS3/PCI_F1 PCI_F2 VDD_PCI VDD_3V66 *FS4/PCI0 3V66_0:2 PCI1 PCI2 GND_PCI VDD_PCI PCI3 PCI_F0:2 PCI4 PCI0:6 PCI5 VDD_48MHz PCI6 3V66_3/48MHz_1 VDD_PCI VTT_PWRGD# VDD_48MHz 48MHz_0 RST# GND_48MHz *FS0/48MHz_0 24_48MHz *FS1/24_48MHz VDD_48MHz VDD_CPU CPU0:1, CPU0:1#, CPU_ITP, CPU_ITP# RST# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/MULTSEL0* GND_REF VDD_CPU CPU_ITP CPU_ITP# GND_CPU PWR_DWN# CPU0 CPU0# VDD_CPU CPU1 CPU1# GND_CPU IREF VDD_CORE GND_CORE VDD_3V66 3V66_0 3V66_1 GND_3V66 3V66_2 3V66_3/48MHz_1 SCLK SDATA ~ SSOP-48 CY28349B Note: 1. Signals marked with ‘*’ and “^” have internal pull-up and pull-down resistors, respectively. Cypress Semiconductor Corporation Document #: 38-07454 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 17, 2002 CY28349B Pin Definitions Pin Name X1 Pin No. 3 Pin Type I Pin Description Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Reference Clock 0/Current Multiplier Selection 0: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows: MULTSEL1:0 00 = Ioh is 4 x IREF 01 = Ioh is 5 x IREF 10 = Ioh is 6 x IREF 11 = Ioh is 7 x IREF Reference Clock 1/Current Multiplier Selection 1: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows: MULTSEL1:0 00 = Ioh is 4 x IREF 01 = Ioh is 5 x IREF 10 = Ioh is 6 x IREF 11 = Ioh is 7 x IREF CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through serial input interface. CPU Clock Output for ITP: Frequency is set by the FS0:4 inputs or through serial input interface. 66-MHz Clock Outputs: 3.3V fixed 66-MHz clock. Free-running PCI Output 0/Frequency Select 2: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. Free-running PCI Output 1/Frequency Select 3: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. Free-running PCI Output 2: 3.3V free-running PCI output. PCI Output 0/Frequency Select 4: 3.3V PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. PCI Clock Output 1 to 6: 3.3V PCI clock outputs. 48MHz Output/Frequency Select 0: 3.3V fixed 48-MHz, non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. This output will be used as the reference clock for USB host controller in Intel 845 (Brookdale) platforms. For Intel Brookdale – G platforms, this output will be used as the VCH reference clock. 24 or 48MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or 48-MHz non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. This output will be used as the reference clock for SIO devices in Intel 845 (Brookdale) platforms. For Intel Brookdale – G platforms, this output will be used as the reference clock for both USB host controller and SIO devices. We recommend system designer to configure this output as 48 MHz and “HIGH Drive” by setting Byte [5], Bit [0] and Byte [9], Bit [7], respectively. X2 REF0/MULTSEL0 4 48 O I/O REF1/MULTSEL1 1 I/O CPU0:1, CPU0:1# www.DataSheet4U.com 41, 38, 40, 37 44, 45 31, 30, 28 6 O I/O O I/O CPU_ITP, CPU_ITP# 3V66_0:2 PCI_F0/FS2 PCI_F1/FS3 7 I/O PCI_F2 PCI0/FS4 8 10 I/O I/O PCI1:6 48MHz_0/FS0 11, 12, 14, 15, 16, 17 22 O I/O 24_48MHz/FS1 23 I/O Document #: 38-07454 Rev. *A Page 2 of 22 CY28349B Pin Definitions (continued) Pin Name 3V66_3/48MHz_1 PWR_DWN# SCLK SDATA RST# Pin No. 27 42 26 25 20 Pin Type O I I I/O Pin Description 48-MHz or 66-MHz Output: 3.3V output. Power-down Control: 3.3V LVTTL compatible input that places the device in power down mode when held low. SMBus Clock Input: Clock pin for serial interface. SMBus Data Input: Data pin for serial interface. O System Reset Output: Open-drain system reset output. (open-d rain) I I Current Reference for CPU Output: A precision resistor is attached to this pin which is connected to the internal current reference. Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL input. VTT_PWRGD# is a level-sensitive strobe used to determine when FS0:4 and MULTSEL0:1 inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. 3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. IREF VTT_PWRGD# 35 19 VDD_REF, VDD _PCI, VDD_48MHz, VDD_3V66, VDD_CPU GND_PCI, GND_48MHz, GND_3V66, www.DataSheet4U.com GND_CPU, GND_REF, VDD_CORE GND_CORE 2, 9, 18, 24, 32, 39, 46 P 5, 13, 21, 29, 36, 43, 47 G Ground Connection: Connect all ground pins to the common system ground plane. 34 33 P G 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. Analog Ground Connection: Ground for core logic, PLL circuitry. Document #: 38-07454 Rev. *A Page 3 of 22 CY28349B Swing Select Functions MULTSEL1 0 0 0 0 1 1 1 1 0 0 0 www.DataSheet4U.com MULTSEL0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω Reference R, IREF = VDD/(3*Rr) Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Output Current IOH = 4*Iref IOH = 4*Iref IOH = 5*Iref IOH = 5*Iref IOH = 6*Iref IOH = 6*Iref IOH = 7*Iref IOH = 7*Iref IOH = 4*Iref IOH = 4*Iref IOH = 5*Iref IOH = 5*Iref IOH = 6*Iref IOH = 6*Iref IOH = 7*Iref IOH = 7*Iref VOH @ Z 1.0V @ 50 1.2V @ 60 1.25V @ 50 1.5V @ 60 1.5V @ 50 1.8V @ 60 1.75V @ 50 2.1V @ 60 0.47V @ 50 0.56V @ 60 0.58V @ 50 0.7V @ 60 0.7V @ 50 0.84V @ 60 0.81V @ 50 0.97V @ 60 0 1 1 1 1 Document #: 38-07454 Rev. *A Page 4 of 22 CY28349B Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can be individually enabled or disabled. The register associated with the Serial Data Interface initializes to its default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts Byte Write, byte read, Block Write and Block Read operation from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The Block Write and Block Read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 6:0 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be ‘0000000’. Descriptions Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 www.DataSheet4U.com Block Read Protocol Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 ... ... ... ... Star