MPEG1 Decoder

www.DataSheet4U.com CXD1856Q/R MPEG1 Decoder Description The CXD1856Q/R is a single-chip MPEG1 decoder with a built-in CD-ROM decoder which allows decoding of MPEG1 system, video and audio layers. A built-in CD-ROM decoder enables direct connection with a CD-DSP. Combining this chip with a control microcomputer and 4-Mbit DRAM, etc. allows configuration of a MPEG1 decoding system for video CD players, etc. Features • Supply voltage: 3.3 ± 0.3V • Input and output voltages: LVTTL compatible • 5V can be applied as the input voltage (excluding some pins) • Allows decoding of MPEG1 system, video and audio layers • Built-in CD-ROM decoder allows direct connection with a CD-DSP • CD-ROM decoded output can be transferred to and stored in an external DRAM • RGB and YCbCr video data output allowed • Built-in video sync generator • Audio data output can support various DAC • Supports various special playback modes • Video CD PAL high resolution still picture can be decoded with a single 4-Mbit DRAM • 8-bit parallel and 4-line serial host interfaces • CD-DA through operation allowed Block Diagram 120 pin QFP (Plastic) 120 pin LQFP (Plastic) Structure Silicon gate CMOS IC Applications Video CD players, MPEG1 decoder boards, etc. CD-DSP I/F CD-ROM Decoder MPEG System Decoder MPEG Audio Decoder Audio I/F To each circuit block MPEG Video Decoder Host interface DRAM Controler Video Postprocessor & Sync Generator Video I/F Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– Video Sync Signal DRAM I/F Host I/F E97815-PS CXD1856Q/R 1. Pin Configuration CBLNK/FSC FID/FHREF XSGRST BCKO DOIN HA0 VDD CSYNC XHIRQ XTL2O XRST XTL2I LRCO BCKI DATO HRW DATI VSS DOUT LRCI VSYNC XHDT VDD CLK0O C2PO HSYNC XHCS HA1 FSXI 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 VSS XTL0O XTL0I VDD HA2 HA3 HD0 HD1 HD2 1 2 3 4 5 6 7 8 9 90 VDD 89 DCLK 88 B/Cb7 87 B/Cb6 86 B/Cb5 85 B/Cb4 84 B/Cb3 83 B/Cb2 82 B/Cb1 81 B/Cb0 80 G/Y7 79 G/Y6 78 G/Y5 77 G/Y4 76 G/Y3 HD3 10 HD4 11 HD5 12 HD6 13 VDD 14 VSS 15 HD7 16 MA3 17 MA4 18 MA2 19 MA5 20 MA1 21 VSS 22 MA6 23 MA0 24 CKEY 25 DTVLD 26 VSS 27 VSS 28 VSS 29 VSS 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS 75 VSS 74 VDD 73 G/Y2 72 G/Y1 71 G/Y0 70 R/Cr7 69 R/Cr6 68 R/Cr5 67 R/Cr4 66 R/Cr3 65 R/Cr2 64 R/Cr1 63 R/Cr0 62 XVOE 61 VSS XMWE OSDEN XCAS0 OSDG OSDR MD11 XRAS MD14 MD9 MD6 MD4 MD1 OSDB MD13 MD8 MA8 VSS MD7 MD2 MA7 VDD MD10 MD12 MD15 VSS MD0 XCAS2/MA9 MD5 –2– MD3 VDD CXD1856Q/R 2. Pin Description Pin No. Symbol VDD VSS 2 3 XTL0O XTL0I O I I I/O +3.3V power supply Connect to ground. Video decoder master clock. Input the clock to XTL0I or connect an oscillator between XTL0I and XTL0O. The recommended frequencies are 27MHz, 28.6363MHz (NTSC 8fsc) and 35.4686MHz (PAL 8fsc). When the host interface operates in parallel mode, these pins are the register address inputs. In serial mode, HA0 is the serial data input, and HA1 to HA3 should be fixed to low level. When the host interface operates in parallel mode, these pins are the register data I/Os. In serial mode, HD0 is the serial data output, and HD1 to HD7 should be fixed to low level. DRAM address signal outputs. Connect to the DRAM address pins so that the numbers match. Row address strobe signal output. Connect to the DRAM RAS signal pin. DRAM write enable signal output. Connect to the DRAM WE signal pin. Used when connecting 8 Mbits of DRAM. Connect to the upper word (256K to 512K-1) DRAM CAS signal pin (for both the upper and lower bytes) when the DRAM configuration is 256 Kwords × 16 bits × 2, and to the MA9 pin (for two DRAMs) when the DRAM configuration is 512 Kwords × 8 bits × 2. DRAM column address strobe signal output. Connect to the lower word (0 to 256K-1) DRAM CAS signal pin (for both the upper and lower bytes) when the DRAM configuration is 256Kwords × 16 bits × 2, and to all DRAM CAS signal pins in all other cases. DRAM data signal I/Os. Connect to the DRAM data pins so that the numbers match. OSD enable signal. The enabled polarity is changed by the register settings. OSD data inputs. When the signal input to the OSDEN pin is enabled, the color registered in the color table which is specified by these three inputs (3 bits) is output as the image data. Video output enable signal. Image data output and DCLK output are enabled when this pin is low, and disabled when this pin is high (high impedance). Note that the output control register must be set to output enable for output to be enabled. Description 5, 6, 119, HA0 to HA3 120 7 to 13, 16 17 to 21, 23, 24, 32, 33 34 35 HD0 to HD7 I/O MA0 to MA8 XRAS XMWE O O O 36 XCAS2/ MA9 O 37 XCAS0 O 38 to 43, 46 to 55 56 MD0 to MD15 OSDEN OSDB, OSDG, OSDR I/O I 57 to 59 I 62 XVOE I 63 to 70 71 to 73, 76 to 88 81 to 88 R/Cr0 to R/Cr7 G/Y0 to G/Y7 B/Cb0 to B/Cb7 DCLK I/O Dot clock (DCLK) signal. The DCLK frequency is normally 13.5MHz. DCLK can be input from this pin, or frequency divided from the clock input and output from this pin. O Image data outputs. The output data format (RGB, YCbCr, etc.) and the correspondence between the pins and output data can be changed by setting the registers. 89 –3– CXD1856Q/R Pin No. 92 Symbol HSYNC I/O I/O Description Horizontal sync signal. When using the built-in sync generator, the dot clock (DCLK) is frequency divided and output. When not using the sync generator, this pin is an input. Vertical sync signal. When using the built-in sync generator, the dot clock (DCLK) is frequency divided and output. When not using the built-in sync generator, this pin is an input. Field identification signal (FID) and horizontal sync phase reference signal (FHREF). The signal to be used is set in the register. When set to FID, this pin is an output if using the built-in sync generator, and an input if not using the built-in sync generator. High corresponds to odd fields. When set to FHREF, this pin outputs the signal obtained by frequency dividing XTL0. When XTL0 is 8fsc, this signal is equivalent to the HSYNC cycle, and can be used for phase comparison with the HSYNC signal. Composite blanking signal (CBLNK) and fsc signal. The signal to be used is set in the register. When set to CBLNK, this pin is an output if using the built-in sync generator, and an input if not using the built-in sync generator. When set to fsc, this pin outputs the signal obtained by frequency dividing XTL0. The frequency division ratio can be selected from 1/8 or 1/16. Composite sync signal obtained by frequency dividing DCLK. This pin cannot be input. Sync generator reset signal input. The built-in sync generator is initialized by setting this pin low. Output for clock obtained by frequency dividing XTL0. The frequency division ratio can be selected from 1, 1/2, 1/4 or 1/8. Audio digital output. Audio serial data output to DAC. L/R clock output to DAC. Bit clock output to DAC. Audio interface clock input. Input 256fs (11.2896MHz), 384fs (16.9344MHz), 512fs (22.5792MHz), or 768fs (33.8688MHz), etc. Master clock for CD-ROM and audio decoders. Input the clock to XTL2I or connect an oscillator between XTL2I and XTL2O. The recommended frequency is 45MHz. Note that this clock is for the internal circuits, and the input and output are not synchronized. C2 pointer input from CD-DSP. Indicates that the DATI input contains an error. LR clock input from CD-DSP. Indicates the L or R channel of DATI. Serial data input from CD-DSP. Bit clock input from CD-DSP. This clock strobes the DATI input. Digital data input from CD-DSP. Chip select signal input during register access. Wait signal output during register access. Host interface operates in parallel mode and the wait signal is output by the register switching during DRAM access. This pin functions as an open drain, and should therefore be pulled up. It should be pulled up when the host interface operates in serial mode as well. 93 VSYNC I/O 94 FID/FHREF I/O 95 CBLNK/ FSC I/O 96 97 98 99 100 101 102 103 106 107 109 110 111 112 113 114 CSYNC XSGRST CLK0O DOUT DATO LRCO BCKO FSXI XTL2O XTL2I C2PO LRCI DATI BCKI DOIN XHCS O I O O O O O I O I I I I I I I 115 XHDT I/O –4– CXD1856Q/R Pin No. 116 117 118 Symbol HRW XHIRQ XRST I/O I O I Description R/W signal input when the host interface operates in parallel mode. Serial clock input in serial mode. Interrupt request signal output. This pin functions as an open drain, and should therefore be pulled up. Hardware reset signal input. All operation is initialized by setting this pin low. Chroma key signal. While the color specified as the key is output, this pin becomes low. When not used, leave this pin open. Video data judgement signal. While the image data within the frame memory is output, this pin becomes high; during the border color output or blanking, low. When not used, leave this pin open. 25 CKEY O 26 DTVLD O –5– CXD1856Q/R 3. Electrical Characteristics 3-1. Absolute Maximum Ratings Item Supply voltage Input pin voltage Input pin voltage Output pin voltage Output pin voltage I/O pin voltage Symbol VDD VI VI VO VO VI/O Rating –0.5 to +4.6 –0.5 to VDD + 0.5 –0.5 to +5.5 –0.5 to VDD + 0.5 –0.5 to +5.5 –0.5 to +5.5 1.0 –20 to +75 –55 to +150 (Ta = 25°C, VSS = 0V) Unit V V V V V V W °C °C ∗1 ∗2 ∗3 ∗4 Remarks Allowable power dissipation PD Operating temperature Storage temperature Topr Tstg ∗1 XTL0I and XTL2I pins ∗2 Input pins other than those in ∗1 above. �