COP472-3 Liquid Crystal Display Controller

COP472-3 Liquid Crystal Display Controller July 1995 COP472-3 Liquid Crystal Display Controller General Description The COP472–3 Liquid Crystal Display (LCD) Controller is a peripheral member of the COPSTM family fabricated using CMOS technology The COP472-3 drives a multiplexed liquid crystal display directly Data is loaded serially and is held in internal latches The COP472-3 contains an on-chip oscillator and generates all the multi-level waveforms for backplanes and segment outputs on a triplex display One COP472-3 can drive 36 segments multiplexed as 3 x 12 (4 digit display) Two COP472-3 devices can be used together to drive 72 segments (3 x 24) which could be an 8 digit display Features Y Y Y Y Y Y Y Y Y Y Direct interface to TRIPLEX LCD Low power dissipation (100 mW typ ) Low cost Compatible with all COPS processors Needs no refresh from processor On-chip oscillator and latches Expandable to longer displays Operates from display voltage MICROWIRETM compatible serial I O 20-pin Dual-In-Line package and 20-pin SO Block Diagram TL DD 6932 – 1 COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation C1996 National Semiconductor Corporation TL DD 6932 RRD-B30M56 Printed in U S A http www national com Absolute Maximum Ratings Voltage at CS DI SK pins Voltage at all other Pins Operating Temperature Range b 0 3V to a 9 5V b 0 3V to VDD a 0 3V Storage Temperature Lead Temp (Soldering 10 Seconds) b 65 C to a 150 C 300 C 0 C to 70 C DC Electrical Characteristics GND e 0V VDD e 3 0V to 5 5V TA e 0 C to 70 C (depends on display characteristics) Parameter Power Supply Voltage VDD Power Supply Current IDD (Note 1) VDD e 5 5V VDD e 3V Input Levels DI SK CS VIL VIH BPA (as Osc in) VIL VIH Output Levels BPC (as Osc Out) VOL VOH Backplane Outputs (BPA BPB BPC) VBPA BPB BPC ON VBPA BPB BPC OFF VBPA BPB BPC ON VBPA BPB BPC OFF Segment Outputs (SA1 E SA4) VSEG ON VSEG OFF VSEG ON VSEG OFF Internal Oscillator Frequency Frame Time (Int Osc d 192) Scan Frequency (1 TSCAN) SK Clock Frequency SK Width DI Data Setup tSETUP Data Hold tHOLD CS tSETUP tHOLD Output Loading Capacitance Note 1 Power supply current is measured in stand-alone mode with all outputs open and all inputs at VDD Note 2 DV e 0 05VDD Conditions Min 30 Max 55 250 100 Units Volts mA mA 0 7 VDD 08 95 06 VDD 04 VDD VDD VDD a DV DV VDD a DV DV VDD a DV VDD VDD a DV 80 12 8 208 250 Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts kHz ms Hz kHz ms ms ns ms ms VDDb0 6 VDDb0 4 During BP a Time During BPb Time During BP a Time During BPb Time VDDb DV VDDb DV 0 VDDb DV 0 VDDb DV VDDb DV VDDb DV 15 24 39 4 17 10 100 10 10 100 pF http www national com 2 Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at CS DI SK Pins Voltage at All Other Pins Operating Temperature Range b 0 3V to a 9 5V b 0 3V to VDD a 0 3V b 40 C to a 85 C Storage Temperature Lead Temperature (Soldering 10 seconds) b 65 C to a 150 C 300 C DC Electrical Characteristics GND e 0V VDD e 3 0V to 5 5V TA e b40 C to a 85 C (depends on display characteristics) Parameter Power Supply Voltage VDD Power Supply Current IDD (Note 1) VDD e 5 5V VDD e 3V Input Levels DI SK CS VIL VIH BPA (as Osc In) VIL VIH Output Levels BPC (as Osc Out) VOL VOH Backplane Outputs (BPA BPB BPC) VBPA BPB BPC ON VBPA BPB BPC OFF VBPA BPB BPC ON VBPA BPB BPC OFF Segment Outputs (SA1 E SA4) VSEG ON VSEG OFF VSEG ON VSEG OFF Internal Oscillator Frequency Frame Time (Int Osc d 192) Scan Frequency (1 TSCAN) SK Clock Frequency SK Width DI Data Setup tSETUP Data Hold tHOLD CS tSETUP tHOLD Output Loading Capacitance Note 1 Power supply current is measured in stand-alone mode with all outputs open and all inputs at VDD Note 2 DV e 0 05 VDD Conditions Min 30 Max 55 300 120 Units Volts mA mA 0 7 VDD 08 95 06 VDD 04 VDD VDD VDD a DV DV VDD a DV DV VDD a DV VDD VDD a DV 80 12 8 208 250 Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts kHz ms Hz kHz ms ms ns ms ms VDDb0 6 VDDb0 4 During BP a Time During BPb Time During BP a Time During BPb Time VDDb DV VDDb DV 0 VDDb DV 0 VDDb DV VDDb DV VDDb DV 15 24 39 4 17 10 100 10 10 100 pF 3 http www national com Dual-In-Line Package Pin CS VDD GND DI SK BPA BPB BPC SA1 E SC4 TL DD 6932–2 Description Chip select Power supply (display voltage) Ground Serial data input Serial clock input Display backplane A (or oscillator in) Display backplane B Display backplane C (or oscillator out) 12 multiplexed outputs Top View Order Number COP472MW-3 or COP472N-3 See NS Package Number M20A or N20A FIGURE 2 Connection Diagram TL DD 6932 – 3 FIGURE 3 Serial Load Timing Diagram TL DD 6932 – 4 FIGURE 4 Backplane and Segment Waveforms TL DD 6932 – 5 FIGURE 5 Typical Display Internal Connections Epson LD-370 http www national com 4 Functional Description The COP472-3 drives 36 bits of display information organized as twelve segments and three backplanes The COP472-3 requires 40 information bits 36 data and 4 control The function of each control bit is described below Display information format is a function of the LCD interconnections A typical segment backplane configuration is illustrated in Figure 5 with this configuration the COP472-3 will drive 4 digits of 9 segments To adapt the COP472-3 to any LCD display configuration the segment backplane multiplex scheme is illustrated in Table I Two or more COP472-3 chips can be cascaded to drive additional segments There is no limit to the number of COP472-3’s that can be used as long as the output loading capacitance does not exceed specification TABLE I COP472-3 Segment Backplane Multiplex Scheme Bit Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Segment Backplane SA1 SB1 SC1 SC1 SB1 SA1 SA1 SB1 SA2 SB2 SC2 SC2 SB2 SA2 SA2 SB2 SA3 SB3 SC3 SC3 SB3 SA3 SA3 SB3 SA4 SB4 SC4 SC4 SB4 SA4 SA4 SB4 BPC BPB BPA BPB BPC BPB BPA BPA BPC BPB BPA BPB BPC BPB BPA BPA BPC BPB BPA BPB BPC BPB BPA BPA BPC BPB BPA BPB BPC BPB BPA BPA Data to Numeric Display SH SG SF SE SD SC SB SA SH SG SF SE SD SC SB SA SH SG SF SE SD SC SB SA SH SG SF SE SD SC SB SA SPA SP2 SP3 SP4 SEGMENT DATA BITS Data is loaded in serially in sets of eight bits Each set of segment data is in the following format SA SB SC SD SE SF SG SH Data is shifted into an eight bit shift register The first bit of the data is for segment H digit 1 The eighth bit is segment A digit 1 A set of eight bits is shifted in and then loaded into the digit one latches The second set of 8 bits is loaded into digit two latches The third set into digit three latches and the fourth set is loaded into digit four latches CONTROL BITS The fifth set of 8 data bits contains special segment data and control data in the following format SYNC Q7 Q6 X SP4 SP3 SP2 SP1 The first four bits shifted in contain the special character segment data The fifth bit is not used The sixth and seventh bits program the COP472-3 as a stand alone LCD driver or as a master or slave for cascading COP472-3’s BPC of the master is connected to BPA of each slave The following table summarizes the function of bits six and seven Q7 1 0 1 Q6 1 1 0 0 Function Slave Stand Alone Not Used Master BPC Output Backplane Output Backplane Output Internal Osc Output Internal Osc Output BPA Output Oscillator Input Backplane Output Oscillator Input Backplane Output Digit 1 Digit 2 0 The eighth bit is used to synchronize two COP472-3’s to drive an 8 -digit display Digit 3 Digit 4 SC1 BPC SC2 BPC SC3 BPC SC4 BPC not used Q6 Q7 SYNC Digit 1 Digit 2 Digit 3 Digit 4 5 http www national com LOADING SEQUENCE TO DRIVE A 4 -DIGIT DISPLAY Steps 1 2 3 4 5 6 0 Turn CE low Clock in 8 bits of data for digit 1 Clock in 8 bits of data for digit 2 Clock in 8 bits of data for digit 3 Clock in 8 bits of data for digit 4 Clock in 8 bits of data for special segment and control function of BPC and BPA 0 1 1 SP4 SP3 SP2 SP1 7 Turn CS high Note CS may be turned high after any step For example to load only 2 digits of data do steps 1 2 3 and 7 CS must make a high to low transition before loading data in order to reset internal counters LOADING SEQUENCE TO DRIVE AN 8 -DIGIT DISPLAY Two or more COP472-3’s may be connected together to drive additional segments An eight digit multiplexed display is shown in Figure 7 The following is the loading sequence to drive an eight digit display using two COP472-3’s The right chip is the master and the left the slave Steps 1 2 3 1 Turn CS low on both COP472-3’s Shift in 32 bits of data for the slave’s four digits Shift in 4 bits of special segment data a zero and three ones 1 1 0 SP4 SP3 SP2 SP1 TL DD 6932 – 6 FIGURE 6 System Diagram – 4 Digit Display This synchronizes both the chips and BPA is oscillator input Both chips are now stopped 4 5 6 7 0 Turn CS high to both chips Turn CS low to master COP472-3 Shift in 32 bits of data for the master’s 4 digits Shift in four bits of special segment data a one and three zeros 0 0 1 SP4 SP3 SP2 SP1 This sets the master COP472-3 to BPA as a normal backplane output and BPC as oscillator output Now both the chips start and run off the same oscillator 8 Turn CS high TL DD 6932 – 7 The chips are now synchronized and driving 8 digits of display To load new data simply load each chip separately in the normal manner keeping the correct status bits to each COP472-3 (0110 or 0001) FIGURE 7 System Diagram – 8 Digit Display http www national com 6 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Molded DIP (M) Order Number COP472MW-3 NS Package Number M20B 7 http www national com COP472-3 Liquid Crystal Display Controller Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Molded DIP (N)