2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

CDCVF857 2.5 V PHASE LOCK LOOP CLOCK DRIVER SCAS047D − MARCH 2003 − REVISED JUNE 2005 D Recommended Applications: − DDR Memory Modules (DDR400/333/266/200) − Zero Delay Fan-Out Buffer Spread Spectrum Clock Compatible Operating Frequency: 60 MHz to 220 MHz Low Jitter (Cycle-Cycle): ±35 ps Low Static Phase Offset: ±50 ps Low Jitter (Period): ±30 ps 1-To-10 Differential Clock Distribution (SSTL2) Best in Class for VOX = VDD/2 ±0.1 V D Operates From Dual 2.6-V or 2.5-V Supplies D Available in a 40-Pin MLF Package, 48-Pin D D D D D TSSOP Package, 56-Ball MicroStar Junior BGA Package Consumes < 100-µA Quiescent Current External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Input Clocks Meets/Exceeds JEDEC Standard (JESD82−1) For DDRI-200/266/333 Specification Meets/Exceeds Proposed DDRI-400 Specification (JESD82−1A) Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low D D D D D D D description The CDCVF857 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state) and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs. When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF857 is also able to track spread spectrum clocking for reduced EMI. Because the CDCVF857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCVF857 is characterized for both commercial and industrial temperature ranges. AVAILABLE OPTIONS TA −40°C to 85°C −40°C to 85°C TSSOP (DGG) CDCVF857DGG (Pb-Free) 40-Pin MLF CDCVF857RTB CDCVF857RHA (Pb-Free, Green) 56-Ball BGA † CDCVF857GQL † Maximum load recommended is 12 pf for 200 MHz. At 12-pf load, maximum TA allowed is 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2005, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDCVF857 2.5 V PHASE LOCK LOOP CLOCK DRIVER SCAS047D − MARCH 2003 − REVISED JUNE 2005 FUNCTION TABLE (Select Functions) INPUTS AVDD GND GND X X 2.5 V (nom) 2.5 V (nom) 2.5 V (nom) PWRDWN H H L L H H X CLK L H L H L H <20 MHz CLK H L H L H L <20 MHz Y[0:9] L H Z Z L H Z H L Z Z H L Z OUTPUTS Y[0:9] FBOUT L H Z Z L H Z FBOUT H L Z Z H L Z Bypassed/Off Bypassed/Off Off Off On On Off PLL DGG PACKAGE (TSSOP) (TOP VIEW) GND Y0 Y0 VDDQ Y1 Y1 GND GND Y2 Y2 VDDQ VDDQ CLK CLK VDDQ AVDD AGND GND Y3 Y3 VDDQ Y4 Y4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND Y5 Y5 VDDQ Y6 Y6 GND GND Y7 Y7 VDDQ PWRDWN FBIN FBIN VDDQ FBOUT FBOUT GND Y8 Y8 VDDQ Y9 Y9 GND RHA/RTB PACKAGE (MLF) (TOP VIEW) Y1 Y1 VDDQ Y0 Y0 Y5 Y5 VDDQ Y6 40 39 38 37 36 35 34 33 32 31 Y6 30 29 28 27 26 25 24 23 22 21 GND Y2 Y2 VDDQ CLK CLK VDDQ AVDD AGND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND Y7 Y7 VDDQ PWRDWN FBIN FBIN VDDQ VDDQ FBOUT FBOUT Y3 Y3 VDDQ Y4 Y4 Y9 Y9 VDDQ Y8 40-pin HP-VFQFP-N (6,0 x 6,0-mm Body Size, 0,5-mm Pitch, M0#220, Variation VJJD-2, E2 = D2 = 2,9 mm ± 0,15 mm) Package Pinouts 48-pin TSSOP (MO-153-ED) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y8 CDCVF857 2.5 V PHASE LOCK LOOP CLOCK DRIVER SCAS047D − MARCH 2003 − REVISED JUNE 2005 MicroStar Junior BGA (GQL) Package (TOP VIEW) V DDQ V DDQ GND GND Y0 Y0 1 A 2 3 4 Y5 5 Y1 Y1 GND GND Y2 Y2 VDDQ VDDQ CLK CLK VDDQ AVDD AGND GND Y3 Y3 B Y5 6 Y6 Y6 NC NC C GND GND Y7 Y7 PWRDN VDDQ FBIN FBIN VDDQ FBOUT FBOUT GND Y8 Y8 D NC NC E NB F NB NB G NC NC H NC NC J K V DDQ V DDQ GND GND Y4 NB = No ball NC = No connection Y4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y9 Y9 3 CDCVF857 2.5 V PHASE LOCK LOOP CLOCK DRIVER SCAS047D − MARCH 2003 − REVISED JUNE 2005 functional block diagram 3 2 37 16 Power Down and Test Logic 5 6 10 9 20 19 22 23 46 47 CLK CLK FBIN FBIN 13 14 36 35 PLL 39 40 29 30 27 26 32 33 44 43 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT PWRDWN AVDD 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCVF857 2.5 V PHASE LOCK LOOP CLOCK DRIVER SCAS047D − MARCH 2003 − REVISED JUNE 2005 Terminal Functions TERMINAL NAME AGND AVDD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND PWRDWN VDDQ Y0, Y0 Y1, Y1 Y2, Y2 Y3, Y3 Y4, Y4 Y5, Y5 Y6, Y6 Y7, Y7 Y8, Y8 Y9, Y9 DGG 17 16 13, 14 35, 36 32, 33 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 37 4, 11, 12, 15, 21, 28, 34, 38, 45 3, 2 5, 6 10, 9 20, 19 22, 23 46, 47 44, 43 39, 40 29, 30 27, 26 RHA/RTB 9 8 5, 6 25, 26 21, 22 1, 10 27 4, 7, 13, 18, 23, 24, 28, 33, 38 37, 36 39, 40 3, 2 12,11 14, 15 34, 35 32, 31 29, 30 19, 20 17, 16 GQL H1 G2 F1, F2 F5, F6 H6, G5 A3, A4, C1, C2, C5, C6, H2, H5, K3, K4 E6 B3, B4, E1, E2, E5, G1, G6, J3, J4 A1, A2 B2, B1 D1, D2 J2, J1 K1, K2 A6, A5 B5, B6 D6, D5 J5, J6 K6, K5 O O O O O O O O O O Buffered output copies of input clock, CLK, CLK I I I O I/O DESCRIPTION Ground for 2.5-V analog supply 2.5-V analog supply Differential clock input Feedback differential clock input Feedback differential clock output Ground Output enable for Y and Y 2.5-V supply absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VDDQ, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0 or VI > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current to GND or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C qJA For TSSOP (DGG) Package (see Note 3) Airflow Low K High K 0 ft/min 150 ft/min 89.1°C/W 78.5°C/W 70°C/W 65.3°C/W qJA For MLF (RHA/RTB) Package Airflow With 4 Thermal Vias 0 ft/min 150 ft/min 44.7°C/W qJA For BGA(GQL) Package (see Note 4) Airflow High K 0 ft/min 150 ft/min 132.2°C/W 126.4°C/W † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. 2. 3. 4. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. This value is limited to 3.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51. Connecting the NC-balls (C3, C4, D3, D4, G3, G4, H3, H4) to a ground plane improves the θJA to 114.8°C/W (0 airflow). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDCVF857 2.5 V PHASE LOCK LOOP CLOCK DRIVER SCAS047D − MARCH 2003 − REVISED JUNE 2005 recommended operating conditions (see Note 5) MIN Supply voltage Low-level input voltage, VIL High-level input voltage, VIH DC input signal voltage (see Note 5) dc Differential input signal voltage, VID (see Note 6) ac CLK, FBIN CLK, FBIN VDDQ AVDD PWRDWN CLK, CLK, FBIN, FBIN PWRDWN PC1600 − PC3200 2.3 VDDQ − 0.12 −0.3 VDDQ/2 + 0.18 1.7 –0.3 0.36 0.7 VDDQ/2 – 0.2 TYP MAX 2.7 2.7 VDDQ/2 – 0.18 0.7 VDDQ + 0.3 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 VDDQ/2 + 0.2 −12 12 1 −40 4 85 V V V V V V mA mA V/ns °C UNIT CLK, CLK, FBIN, FBIN Input differential pair cross voltage, VIX (see Notes 7 and 8) High-level output current, IOH Low-level output current, IOL Input slew rate, SR Operating free-air temperature, TA NOTES: 5. The unused inputs must be held high or low to prevent them from floating. 6. The dc input signal voltage specifies the allowable dc execution of the differential input. 7. The differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 8. The differential cross-point voltage is expected to track variations of VCC and is the volt