2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

CDCVF855 www.ti.com SCAS839A – APRIL 2007 – REVISED MAY 2007 2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER FEATURES • • • • • • • • • • • Spread-Spectrum Clock Compatible Operating Frequency: 60 MHz to 220 MHz Low Jitter (Cycle-Cycle): ±60 ps (±40 ps at 200 MHz) Low Static Phase Offset: ±50 ps Low Jitter (Period): ±60 ps (±30 ps at 200 MHz) 1-to-4 Differential Clock Distribution (SSTL2) Best in Class for VOX = VDD/2 ±0.1 V Operates From Dual 2.6-V or 2.5-V Supplies Available in a 28-Pin TSSOP Package Consumes < 100-µA Quiescent Current External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Input Clocks Meets/Exceeds JEDEC Standard (JESD82-1) For DDRI-200/266/333 Specification Meets/Exceeds Proposed DDRI-400 Specification (JESD82-1A) Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low DESCRIPTION The CDCVF855 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to 4 differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state) and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency-detection circuit detects the low-frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs. When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF855 is also able to track spread-spectrum clocking for reduced EMI. Because the CDCVF855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCVF855 is characterized for both commercial and industrial temperature ranges. • • • APPLICATIONS • • DDR Memory Modules (DDR400/333/266/200) Zero-Delay Fan-Out Buffer AVAILABLE OPTIONS TA –40°C to 85°C TSSOP (PW) CDCVF855PW Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated CDCVF855 www.ti.com SCAS839A – APRIL 2007 – REVISED MAY 2007 FUNCTION TABLE (Select Functions) INPUTS AVDD GND GND X X 2.5 V (nom) 2.5 V (nom) 2.5 V (nom) PWRDWN H H L L H H X CLK L H L H L H <20 MHz CLK H L H L H L <20 MHz Y[0:3] L H Z Z L H Z H L Z Z H L Z OUTPUTS Y[0:3] FBOUT L H Z Z L H Z FBOUT H L Z Z H L Z Bypassed/off Bypassed/off Off Off On On Off PLL PW PACKAGE (TOP VIEW) GND Y0 Y0 VDDQ GND CLK CLK VDDQ AVDD AGND VDDQ Y1 Y1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND Y3 Y3 VDDQ PWRDWN FBIN FBIN VDDQ FBOUT FBOUT VDDQ Y2 Y2 GND P0043-02 FUNCTIONAL BLOCK DIAGRAM 3 2 PWRDWN AVDD 24 9 Powerdown and Test Logic 12 13 17 16 26 27 6 7 23 22 B0196-02 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 FBOUT FBOUT CLK CLK FBIN FBIN 19 20 PLL 2 Submit Documentation Feedback CDCVF855 www.ti.com SCAS839A – APRIL 2007 – REVISED MAY 2007 Table 2. TERMINAL FUNCTIONS TERMINAL NAME AGND AVDD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND PWRDWN VDDQ Y0, Y0 Y1, Y1 Y2, Y2 Y3, Y3 10 9 6, 7 22, 23 19, 20 1, 5, 14, 15, 28 24 4, 8, 11, 18, 21, 25 2, 3 12, 13 16, 17 26, 27 NO. I/O – – I I O – I – O O O O DESCRIPTION Ground for 2.5-V analog supply 2.5-V analog supply Differential clock input Feedback differential clock input Feedback differential clock output Ground Output enable for Y and Y 2.5-V supply Buffered output copies of input clock, CLK, CLK Buffered output copies of input clock, CLK, CLK Buffered output copies of input clock, CLK, CLK Buffered output copies of input clock, CLK, CLK ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VDDQ, AVDD VI VO IIK IOK IO IDDS Tstg (1) (2) (3) Supply voltage range Input voltage range (2) (3) Output voltage range (2) (3) Input clamp current Output clamp current Continuous output current Continuous current to GND or VDDQ Storage temperature range VI < 0 or VI > VDDQ VO < 0 or VO > VDDQ VO = 0 to VDDQ (1) 0.5 V to 3.6 V –0.5 V to VDDQ + 0.5 V –0.5 V to VDDQ + 0.5 V ±50 mA ±50 mA ±50 mA ±100 mA –65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. This value is limited to 3.6 V maximum. THERMAL CHARACTERISTICS RθJA for TSSOP Package (1) Airflow 0 ft/min (0 m/min) 150 ft/min (45.72 m/min) (1) The package thermal impedance is calculated in accordance with JESD 51. High K 94.4°C/W 82.8°C/W Submit Documentation Feedback 3 CDCVF855 www.ti.com SCAS839A – APRIL 2007 – REVISED MAY 2007 RECOMMENDED OPERATING CONDITIONS MIN Supply voltage VIL VIH Low-level input voltage High-level input voltage DC input signal voltage (1) DC VID Differential input signal voltage (2) AC VIX IOH IOL SR TA (1) (2) (3) (4) Input differential pair cross voltage (3) (4) High-level output current Low-level output current Input slew rate Operating free-air temperature 1 –40 CLK, FBIN CLK, FBIN VDDQ = 2.3 V – 2.7V VDDQ = 2.425 V – 2.7 V VDDQ = 2.3 V – 2.7 V VDDQ = 2.425 V – 2.7 V VDDQ PC1600 – PC3200 AVDD CLK, CLK, FBIN, FBIN PWRDWN CLK, CLK, FBIN, FBIN PWRDWN –0.3 VDDQ/2 + 0.18 1.7 –0.3 0.36 0.25 0.7 0.49 VDDQ/2 – 0.2 VDDQ + 0.3 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 VDDQ + 0.6 VDDQ + 0.6 VDDQ/2 + 0.2 –12 12 4 85 V mA mA V/ns °C V 2.3 VDDQ – 0.12 NOM MAX 2.7 2.7 VDDQ/2 – 0.18 0.7 UNIT V V V V The unused inputs must be held high or low to prevent them from floating. The dc input signal voltage specifies the allowable dc execution of the differential input. The differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. The differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must cross. ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL VOD VOX II IOZ IDDPD AIDD CI (1) (2) (3) Input voltage, all inputs High-level output voltage Low-level output voltage Output voltage swing (3) (2) TEST CONDITIONS VDDQ = 2.3 V, II = –18 mA VDDQ = min to max, IOH = –1 mA VDDQ = 2.3 V, IOH = –12 mA VDDQ = min to max, IOL = 1 mA VDDQ = 2.3 V, IOL = 12 mA Differential outputs are terminated with 120 Ω, CL = 14 pF (See Figure 3) VDDQ = 2.7 V, VI = 0 V to 2.7 V VDDQ = 2.7 V, VO = VDDQ or GND CLK and CLK = 0 MHz; PWRDWN = Low; Σ of IDD and AIDD fO = 170 MHz fO = 200 MHz VDDQ = 2.5 V, VI = VDDQ or GND MIN VDDQ – 0.1 1.7 TYP (1) MAX –1.2 UNIT V V 0.1 0.6 1.1 VDDQ/2 – 0.1 VDDQ/2 VDDQ – 0.4 VDDQ/2 + 0.1 ±10 ±10 20 6 8 2 2.5 100 8 10 3.5 V V V µA µA µA mA pF Output differential cross-voltage Input current High-impedance-state output current Power-down current on VDDQ + AVDD Supply current on AVDD Input capacitance All typical values are at a nominal VDDQ. The differential output signal voltage specifies the differential voltage |VTR – VCP|, where VTR is the true output level and VCP is the complementary output level. The differential cross-point voltage tracks variations of VDDQ and is the voltage at which the differential signals must cross. 4 Submit Documentation Feedback CDCVF855 www.ti.com SCAS839A – APRIL 2007 – REVISED MAY 2007 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER Without load IDD Dynamic current on VDDQ Differential outputs terminated with 120 Ω, CL = 0 pF Differential outputs terminated with 120 Ω, CL = 14 pF ∆C CI(∆) Part-to-part input capacitance variation Input capacitance difference between CLK and CLK, FBIN and FBIN VDDQ = 2.5 V, VI = VDDQ or GND VDDQ = 2.5 V, VI = VDDQ or GND TEST CONDITIONS fO = 170 MHz fO = 200 MHz fO = 170 MHz fO = 200 MHz fO = 170 MHz fO = 200 MHz MIN TYP (1) MAX 80 90 140 150 160 170 1 0.25 UNIT 65 75 110 120 130 140 mA pF pF TIMING REQUIREMENTS over recommended ranges of supply voltage and operating free-air temperature PARAMETER fCLK Operating clock frequency Application clock frequency Input clock duty cycle Stabilization time (PLL mode) (1) Stabilization time (bypass mode) (2) (1) MIN 60 90 40% MAX 220 220 60% 10 30 µs ns UNIT MHz (2) The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input mod