PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER

CDCLVD110A www.ti.com SCAS841 – FEBRUARY 2007 PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER FEATURES • • • • • Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs VCC range 2.5 V ±5% Typical Signaling Rate Capability of Up to 1.1 GHz Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs Full Rail-to-Rail Common-Mode Input Range Receiver Input Threshold ±100 mV Available in 32-Pin TQFP Package Fail-Safe I/O-Pins for VDD = 0 V (Power Down) • • • • DESCRIPTION The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0–Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines. When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled. The CDCLVD110A has an improved startup circuit that minimizes enabling time in AC- and DC-coupled systems. The CDCLVD110A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated CDCLVD110A www.ti.com SCAS841 – FEBRUARY 2007 FUNCTIONAL BLOCK DIAGRAM 2 Submit Documentation Feedback CDCLVD110A www.ti.com SCAS841 – FEBRUARY 2007 TERMINAL FUNCTIONS TERMINAL NAME CK SI CLK0 CLK0 VBB CLK1 CLK1 EN VSS VDD Q [9:0] NO. 1 2 3 4 5 6 7 8 9, 25 16, 32 11, 13, 15, 18, 20, 22, 24, 27, 29, 31 10, 12, 14, 17, 19, 21,23, 26, 28, 30 O I/O I I I I O I I I DESCRIPTION Control register input clock, features a 120-k. pullup resistor Control register serial input/CLK Select, features a 120-k. pulldown resistor True differential input, LVDS Complementary differential input, LVDS Reference voltage output True differential input, LVDS Complementary differential input, LVDS Control enable (for programmability), features a 120-k. pulldown resistor, input Device ground Supply voltage Clock outputs, these outputs provide low-skew copies of CLKIN Q[9:0] O Complementary clock outputs, these outputs provide low-skew copies of CLKIN ABSOLUTE MAXIMUM RATINGS (1) VALUE VDD VI VO Qn, Qn, IOSD Supply voltage Input voltage VI Output voltage Driver short circuit current Electrostatic discharge (HBM 1.5 kΩ, 100 pF), ESD (1) –0.3 to 2.8 –0.2 to (VDD + 0.2) –0.2 to (VDD + 0.2) Continuous >2000 V UNIT V V V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VDD VIC TA Supply voltage Receiver common-mode input voltage Operating free-air temperature 2.375 0.5|VID| –40 NOM 2.5 MAX 2.625 VDD– 0.5|VID| 85 UNIT V V °C Submit Documentation Feedback 3 CDCLVD110A www.ti.com SCAS841 – FEBRUARY 2007 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER DRIVER |VOD| ∆VOD VOS ∆VOS IOS VBB CO VIDH VIDL |VID| IIH IIL CI Differential output voltage VOD magnitude change Offset voltage VOS magnitude change Output short circuit current Reference output voltage Output capacitance Input threshold high Input threshold low Input differential voltage Input current, CLK0/CLK0, CLK1/CLK1 Input capacitance Full loaded IDD VI = VDD VI = 0 V VI = VDD or GND All outputs enabled and loaded, RL = 100 Ω, f = 100 MHz All outputs enabled and loaded, RL = 100 Ω, f = 800 MHz No load IDDZ 3-State Outputs enabled, no output load, f = 0 Hz All outputs 3-state by control logic, f = 0 Hz –100 200 –5 3 100 150 110 160 35 35 5 VO = 0 V |VOD| = 0 V VDD = 2.5 V, IBB = –100 µA VO = VDD or GND 1.15 1.25 3 100 – 40°C to 85  C 0.95 1.2 RL = 100Ω 250 450 600 50 1.45 350 –20 20 1.35 mV mV V mV mA V pF mV mV mV µA pF TEST CONDITIONS MIN TYP MAX UNIT RECEIVER SUPPLY CURRENT Supply current mA LVDS — SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, VDD = 2.5 V ±5% PARAMETER tPLH tPHL tduty tsk(o) tsk(p) tr tf fclk Propagation delay low-to-high Propagation delay high-to-low Duty cycle Output skew Pulse skew Output rise time, 20% to 80%, RL = 100 Ω, CL = 5 pF Output fall time, 20% to 80%, RL = 100 Ω, CL = 5 pF Max input frequency CLK0, CLK0 CLK1, CLK1 FROM (INPUT) CLK0, CLK0 CLK1, CLK1 CLK0, CLK0 CLK1, CLK1 CLK0, CLK0 CLK1, CLK1 TO (OUTPUT) Qn, Qn Qn, Qn Qn, Qn Any Qn, Qn Any Qn, Qn Any Qn, Qn Any Qn, Qn Any Qn, Qn Any Qn, Qn 900 1100 45% 30 50 600 350 350 MIN TYP 2 2 MAX 3 3 55% ps ps ps ps ps MHz UNIT ns ns tsk(pp) Part-to-part skew 4 Submit Documentation Feedback CDCLVD110A www.ti.com SCAS841 – FEBRUARY 2007 CONTROL REGISTER CHARACTERISTICS over recommended operating free-air temperature range, VDD = 2.5 V ±5% (unless otherwise noted) PARAMETER fMAX tsu th tremoval tstartup tw VIH VIL IIH IIL Maximum frequency of shift register Setup time, clock to SI Hold time, clock to SI Removal time, enable to clock Startup time after disable through SI Clock pulse width, minimum Logic input high Logic input low Input current, CK pin Input current, SI and EN pins Input current, CK pin Input current, SI and EN pins VDD = 2.5 V VDD = 2.5 V VI = VDD VI = GND –5 10 –10 –5 3 2 0.8 5 –30 30 5 TEST CONDITIONS MIN 100 TYP 150 2 1.5 1.5 1.0 MAX UNIT MHz ns ns ns µs ns V V µA µA Submit Documentation Feedback 5 CDCLVD110A www.ti.com SCAS841 – FEBRUARY 2007 SPECIFICATION OF CONTROL REGISTER The CDCLVD110A has an 11-bit, serial-in shift register and an 11-bit control register. The control Register enables/disables each output clock, and selects either CLK0 or CLK1 as the input clock. The CDCLVD110A has two modes of operation: Programmable Mode (EN=1) The shift register uses a serial input (SI) and a clock input (CK). Once the shift register is loaded with 11 clock pulses, the 12th clock pulse loads the control register. The first bit (bit 0) on SI enables the Q9-Q9 output pair, and the 10th bit (bit 9) enables the Q0-Q0 pair. The 11th bit (bit 10) on SI selects either CLK0 or CLK1 as the input clock; a bit value of 0 selects CLK0, whereas a bit value of 1 selects CLK1. To restart the control register configuration, a reset of the state machine must be done with a clock pulse on CK (shift register clock input) and EN set to low. The control register can be configured only once after each reset. Standard Mode (EN=0) In this mode, the CDCLVD110A is not programmable and all the clock outputs are enabled. The clock input (CLK0 or CLK1) is selected with the SI pin, as is shown in the table entitled control register. STATE-MACHINE INPUTS EN L L H H L SI L H L H X CK X X ↑ OUTPUT All outputs enabled, CLK0 selected, control register disabled, default state All outputs enabled, CLK1 selected, control register disabled First stage stores L, other stage stores data of previous stage First stage stores H, other stage stores data of previous stage Reset of state machine, shift and control registers CONTROL REGISTER BIT 10 L H X BITS [0-9] H H L QN[0-9] CLK0 CLK1 Outputs disabled SERIAL INPUT (SI) SEQUENCE BIT 10 CLK_SEL BIT 9 Q0 BIT 8 Q1 BIT 7 Q2 BIT 6 Q3 BIT 5 Q4 BIT 4 Q5 BIT 3 Q6 BIT 2 Q7 BIT 1 Q8 BIT 0 Q9 TRUTH TABLE FOR CONTROL LOGIC CK L L L L L L EN L L L L L L SI L L L H H H CLK0 L H Open X X X CLK0 H L Open X X X CLK1 X X X L H Open X = Don't care CLK1 X X X H L Open Q(0-9) L H L L H L Q(0-9) H L H H L H All outputs enabled 6 Submit Documentation Feedback CDCLVD110A www.ti.com SCAS841 – FEBRUARY 2007 APPLICATION INFORMATION Fall-Safe Information For VDD = 0 V (power-down mode) the CDCLVD110A has fail-safe input and output pins. In power-on mode, fail-safe biasing at input pins can be accomplished with a 10-kΩ pullup resistor from CLK0/CLK1 to VDD and a 10-kΩ pulldown resistor from CLK0/CLK1 to GND. LVDS Receiver Input Termination The LVDS receiver inputs require 100-Ω termination resistors placed as close as possible across the input pins. Control Inputs Termination No external termination is required. The CK control input has an internal 120-kΩ pullup resistor, while the SI– and EN–control inputs each have an internal 120-kΩ pulldown resistor. If the control pins are left open per the default, all outputs are enabled, CLK0, CLK0 is selected, and the control register is disabled. Submit Documentation Feedback 7 CDCLVD110A www.ti.com SCAS841 – FEBRUARY 2007 PARAMETER MEASUREMENT INFORMATION A. Output skew, tsk(o), is calculated as the greater of: – The difference between the fastest and the slowest tPLHn (n = 1, 2,...10) – The difference between the fastest and the slowest tPHLn (n = 1, 2,...10) Part-to-part skew, tsk(pp), is calculated as the greater of: – The difference between the fastest and the slowest tPLHn (n = 1, 2,...10) across multiple devices – The difference between the fastest and the slowest tPHLn (n = 1, 2,...10) across multiple devices Pulse ske