High-Performance Clock Distributor

CDCL1810 www.ti.com SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007 1.8V, 10 Output, High-Performance Clock Distributor FEATURES • • • • • Single 1.8V Supply High-Performance Clock Distributor with 10 Outputs Low Input-to-Output Additive Jitter: As Low As 10fs RMS Output Group Phase Adjustment Low-Voltage Differential Signaling (LVDS) Input, 100Ω Differential On-Chip Termination, Up to 650MHz Frequency Differential Current Mode Logic (CML) Outputs, 50Ω Single-Ended On-Chip Termination, Up to 650MHz Frequency Two Groups of Five Outputs Each with Independent Frequency Division Ratios Output Frequency Derived with Divide Ratios of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80 Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements Power Consumption: 410mW Typical • • • • • • Output Enable Control for Each Output SDA/SCL Device Management Interface 48-pin QFN (RGZ) Package Industrial Temperature Range: –40°C to +85°C APPLICATIONS Clock Synthesis and Distribution for High-Speed SERDES Synthesis and Distribution of SERDES Reference Clocks for 1G/10G Ethernet, 1X/2X/4X/10X Fibre Channel, PCI Express, Serial ATA, SONET, CPRI, OBSAI, etc. Up to 1-to-10 Clock Buffering and Fan-out • • • • • • DIVIDER Differential LVDS Input Up to 650MHz 5 Differential CML Outputs Up to 650MHz DIVIDER SDA/SCL 5 Differential CML Outputs Up to 650MHz Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated CDCL1810 www.ti.com SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007 DESCRIPTION The CDCL1810 is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: FOUT = FIN/P Where: P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80 The CDCL1810 supports one differential LVDS clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDS receivers if they are ac-coupled. With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810 can support a single-ended clock input as outlined in the Pin Description Table. All device settings are programmable through the SDA/SCL, serial two-wire interface. The phase of one output group relative to the other can be adjusted through the SDA/SCL interface. For post-divide ratios (P0, P1) that are multiples of 5, the total number of phase adjustment steps (n) equals the divide-ratio divided by 5. For post-divide ratios (P0, P1) that are not multiples of 5, the total number of steps (n) is the same as the post-divide ratio. The phase adjustment step (∆Φ) in time units is given as: ∆Φ = 1/(n × FOUT) where FOUT is the respective output frequency. The device operates in a 1.8V supply environment and is characterized for operation from –40°C to +85°C. The CDCL1810 is available in a 48-pin QFN (RGZ) package. 2 Submit Documentation Feedback CDCL1810 www.ti.com SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS (1) TA –40°C to +85°C –40°C to +85°C (1) PACKAGED DEVICES CDCL1810RGZT CDCL1810RGZR FEATURES 48-pin QFN (RGZ) Package, small tape and reel 48-pin QFN (RGZ) Package, tape and reel For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). VALUE VDD, AVDD VLVDS VI ESD TJ TSTG (1) (2) Supply voltage (2) Voltage range at LVDS input pins (2) Voltage range at all non-LVDS input pins (2) Electrostatic discharge (HBM) Junction temperature Storage temperature range –0.3 to 2.5 –0.3 to 4.0 –0.3 to 3.0 2 +125 –65 to +150 UNIT V V V kV °C °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted). MIN VDD AVDD TA TJ θJA Digital supply voltage Analog supply voltage Ambient temperature (no airflow, no heatsink) Junction temperature Junction-to-ambient thermal resistance (1): airflow = 0 lfm airflow = 50 lfm (1) 28.3 22.4 °C/W 1.7 1.7 –40 NOM 1.8 1.8 MAX 1.9 1.9 +85 +105 UNIT V V °C °C No heatsink; power uniformly distributed; 36 ground vias (6 x 6 array) tied to the thermal exposed pad; 4-layer high-K board. Submit Documentation Feedback 3 CDCL1810 www.ti.com SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions (unless otherwise noted). PARAMETER IVDD IAVDD VIL,CMOS VIH,CMOS IIL,CMOS IIH,CMOS VOL,SDA IOL,CMOS Total current from digital 1.8V supply Total current from analog 1.8V supply Low level CMOS input voltage High level CMOS input voltage Low level CMOS input current High level CMOS input current Low level CMOS output voltage for the SDA pin Low level CMOS output current TEST CONDITIONS All outputs enabled; VDD = VDD,typ 650MHz LVDS input All outputs enabled; AVDD = VDD,typ 650MHz LVDS input VDD = 1.8V VDD = 1.8V VDD = VDD,max, VIL = 0.0V VDD = VDD,max, VIH = 1.9V Sink current = 3 mA 0 –0.2 VDD –0.6 MIN TYP 212 16 0.6 VDD –120 65 0.2VDD 8 MAX UNIT mA mA V V µA µA V mA AC ELECTRICAL CHARACTERISTICS Over recommended operating conditions (unless otherwise noted). PARAMETER ZD,IN VCM,IN VS,IN VD,IN tR,OUT, tF,OUT VCM,OUT VS,OUT VD,OUT FIN FOUT Differential input impedance for the LVDS input terminals Common-mode voltage, LVDS input Single-ended LVDS input voltage swing Differential LVDS input voltage swing Output signal rise/fall time Common-mode voltage, CML outputs Single-ended CML output voltage swing Differential CML output voltage swing Clock input frequency Clock output frequency ac-coupled ac-coupled 20%–80% VDD – 0.31 180 360 TEST CONDITIONS MIN 90 1125 100 200 100 VDD – 0.23 230 460 VDD – 0.19 280 560 650 650 1200 TYP MAX 132 1375 600 1200 UNIT Ω mV mVPP mVPP ps V mVPP mVPP MHz MHz 4 Submit Documentation Feedback CDCL1810 www.ti.com SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007 AC ELECTRICAL CHARACTERISTICS (continued) Over recommended operating conditions (unless otherwise noted). PARAMETER JOUT Additive clock output jitter TEST CONDITIONS FIN = 30.72MHz, FOUT = 30.72MHz VD,IN = 200mVPP 10Hz–1MHz offset 1MHz–5MHz offset 12kHz–5MHz offset FIN = 30.72MHz, FOUT = 30.72MHz VD,IN = 1200mVPP 10Hz–1MHz offset 1MHz–5MHz offset 12kHz–5MHz offset FIN = 650MHz, FOUT = 650MHz VD,IN = 200mVPP 10Hz–1MHz offset 1MHz–20MHz offset 12kHz–20MHz offset FIN = 650MHz, FOUT = 650MHz VD,IN = 1200mVPP 10Hz–1MHz offset 1MHz–20MHz offset 12kHz–20MHz offset TP TSOUT Input-to-output delay Clock output skew FIN = 30.72MHz, FOUT = 30.72MHz YP[9:0] outputs FIN = 30.72MHz, FOUT = 30.72MHz YP[9:0] outputs relative to YP[0] –64 12 23 27 3 64 fs RMS fs RMS fs RMS ns ps 27 66 72 fs RMS fs RMS fs RMS 257 500 570 fs RMS fs RMS fs RMS 188 480 514 fs RMS fs RMS fs RMS MIN TYP MAX UNIT AC ELECTRICAL CHARACTERISTICS FOR THE SDA/SCL INTERFACE (1) PARAMETER fSCL th(START) tw(SCLL) tw(SCLH) tsu(START) th(SDATA) tsu(DATA) tr(SDATA) tf(SDATA) tsu(STOP) tBUS (1) SCL frequency START hold time SCL low-pulse duration SCL high-pulse duration START setup time SDA hold time SDA setup time SCL / SDA input rise time SCL / SDA input fall time STOP setup time bus free time See Figure 3 for the timing behavior. 0.6 1.3 0.6 1.3 0.6 0.6 0 0.6 0.3 0.3 MIN TYP MAX 400 UNIT kHz µs µs µs µs µs µs µs µs µs µs Submit Documentation Feedback 5 CDCL1810 www.ti.com SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007 DEVICE INFORMATION 48-PIN QFN (RGZ) (TOP VIEW) YP8 ADD1 37 AVDD AVDD YN9 YN8 39 YP9 NC 42 48 47 46 45 44 43 41 40 38 VDD VDD NC NC NC AVDD CLKP CLKN AVDD YP0 YN0 VDD YP1 YN1 VDD VSS 1 2 3 4 5 6 36 35 34 33 32 31 ADD0 VDD YN7 YP7 VDD YN6 YP6 VDD YN5 YP5 VDD SDA CDCL1810 7 8 9 10 11 12 30 29 28 27 26 25 20 21 22 23 VDD 13 14 15 16 17 18 NC YP2 YP3 YN2 YN3 19 YP4 YN4 VDD VDD VDD NOTE: Exposed thermal pad must be soldered to VSS. The CDCL1810 is available in a 48-pin QFN (RGZ) package with a pin pitch of 0,5mm. The exposed thermal pad serves both thermal and electrical grounding purposes. NOTE: The device must be soldered to ground (VSS) using as many ground vias as possible. The device performance will be severely impacted if the exposed thermal pad is not grounded appropriately. 6 Submit Documentation Feedback SCL 24 CDCL1810 www.ti.com SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS TERMINAL NAME V