Crystal-Oscillator Clock Generator

CDCE421 www.ti.com SCAS842 – APRIL 2007 Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator FEATURES • • Single 3.3V Supply High-Performance Clock Generator Incorporating Crystal-Oscillator Circuitry With Integrated Frequency Synthesizer Low-Output Jitter, as Low as 380 fs (rms Integrated Between 10 kHz–20 MHz) Low Phase Noise at High Frequency; at 708 MHz It Is Less Than –109 dBc/Hz at 10-kHz and –146 dBc/Hz at 10-MHz Offset From the Carrier Supports Crystal Frequencies Between 27.35 MHz to 38.33 MHz Output Frequency Ranges From 10.9 MHz up to 766.7 MHz and From 875.2 MHz up to 1175 MHz Low-Voltage Differential Signaling (LVDS) Output, 100-Ω Differential Off-Chip Termination, 10.9-MHz to 400-MHz Frequency Range A A A • • • • • • • • • • • • • • • • Differential Low-Voltage Positive Emitter-Coupled Logic (LVPECL) Output, 10.9-MHz to 1.175-GHz Frequency Range Two Fully Integrated Voltage-Controlled Oscillators (VCOs) Support Wide Output Frequency Range Fully Integrated Programmable Loop Filter Typical Power Consumption 240 mW in LVDS Mode and 300 mW in LVPECL Mode Chip-Enable Control Pin Simple Serial Interface Allows Programming After Manufacturing Integrated On-Chip Non-Volatile Memory (EEPROM) to Store Settings Without the Need to Apply High Voltage to the Device Die or QFN24 Package ESD Protection Exceeds 2 kV HBM Industrial Temperature Range –40°C to 85°C APPLICATIONS Low-Cost, High-Frequency Crystal Oscillator CE SDATA Output Enable/Programming Interface and EEPROM for Configuration Settings Loop Filter PFD/Charge Pump VCO 1 Feedback Divider Prescaler X-tal LVPECL or LVDS Output Divider Crystal Oscillator Input CLK NCLK VCO 2 B0216-01 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated CDCE421 SCAS842 – APRIL 2007 www.ti.com DESCRIPTION The CDCE421 is a high-performance, low-phase-noise clock generator. It has two fully integrated, low-noise, LC-based voltage controlled oscillators (VCOs) that operate in the 1.750-GHz–2.350-GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for the PLL-based frequency synthesizer. The output frequency (fout) is proportional to the frequency of the input crystal (fxtal). The prescaler divider, feedback divider, output divider, and VCO selection are what set (fout) with respect to (fxtal). For a desired frequency (fout), look in Table 1 and find the corresponding settings in the same row. Use Equation 1 to calculate the exact crystal oscillator frequency needed for the desired output. f xtal + OutputDivider FeedbackDivider f out (1) Output divider(1) = 1, 2, 4, 8, 16, or 32 Feedback divider(2) = 12, 16, 20, or 32 (1)Output divider and feedback divider should be from the same row in Table 1. (2)Feedback divider is set automatically with respect to the prescaler setting in Table 1. A high-level block diagram of the CDCE421 is shown in Figure 1. The CDCE421 supports one differential LVDS clock output or one differential LVPECL output. All device settings are programmable through a Texas Instruments proprietary simple serial interface. The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C. The CDCE421 is available in die form or in a QFN-24 package. XIN 1 XIN 2 Crystal Oscillator Loop Filter PFD/ Charge Pump VCO 1 1890 VCO 2 2200 Feedback Divider 12, 16, 20 and 32 LVPCL Prescaler 2, 3, 4 and 5 CE 1-Pin Interface and Control SDATA LVDS EEPROM Output Divider 1, 2, 4, 8, 16 and 32 B0217-01 Figure 1. High-Level Block Diagram of the CDCE421 In the CDCE421, the feedback divider is set automatically with respect to the prescaler setting. The product of the prescaler and the feedback divider will be either 60 or 64, as shown in Table 1, to keep the control loop stable. 2 Submit Documentation Feedback www.ti.com CDCE421 SCAS842 – APRIL 2007 DEVICE SETUP AND CONFIGURATION Table 1. Crystal Frequency Selection and Device Settings DESIRED OUTPUT FREQUENCY (MHz) From 1020.0 875.2 (2) REQUIRED INPUT CRYSTAL FREQUENCY (MHz) From 31.875 27.351 32.500 29.174 31.875 27.351 34.000 29.174 34.000 29.174 31.875 27.351 34.000 29.174 34.000 29.174 31.875 27.351 34.000 29.174 34.000 29.174 31.875 27.351 34.000 29.174 34.000 29.174 31.875 27.351 34.000 29.174 34.000 29.174 31.875 27.351 34.000 29.174 To 36.719 31.875 38.333 32.500 36.719 31.875 38.333 34.000 38.333 34.000 36.719 31.875 38.333 34.000 38.333 34.000 36.719 31.875 38.333 34.000 38.333 34.000 36.719 31.875 38.333 34.000 38.333 34.000 36.719 31.875 38.333 34.000 38.333 34.000 36.719 31.875 38.333 34.000 VCO SELECTION VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 VCO 2 VCO 1 OUTPUT DIVIDER 1 1 1 1 1 1 1 1 2 2 2 2 2 2 4 4 4 4 4 4 8 8 8 8 8 8 16 16 16 16 16 16 32 32 32 32 32 32 PRESCALER SETTING 2 2 3 3 4 4 5 5 3 3 4 4 5 5 3 3 4 4 5 5 3 3 4 4 5 5 3 3 4 4 5 5 3 3 4 4 5 5 FEEDBACK DIVIDER (1) 32 32 20 20 16 16 12 12 20 20 16 16 12 12 20 20 16 16 12 12 20 20 16 16 12 12 20 20 16 16 12 12 20 20 16 16 12 12 To 1175.0 1020.0 766.7 (2) 650.0 583.5 510.0 437.6 408.0 350.1 340.0 291.7 255.0 218.8 204.0 175.0 170.0 145.9 127.5 109.4 102.0 87.5 85.0 72.9 63.8 54.7 51.0 43.8 42.5 36.5 31.9 27.4 25.5 21.9 21.3 18.2 15.9 13.7 12.8 10.9 (1) (2) 650.0 587.5 510.0 460.0 408.0 383.3 340.0 293.8 255.0 230.0 204.0 191.7 170.0 146.9 127.5 115.0 102.0 95.8 85.0 73.4 63.8 57.5 51.0 47.9 42.5 36.7 31.9 28.8 25.5 24.0 21.3 18.4 15.9 14.4 12.8 The feedback divider is set automatically with respect to the prescaler setting. Discontinuity in frequency range Submit Documentation Feedback 3 CDCE421 SCAS842 – APRIL 2007 www.ti.com DEVICE SETUP EXAMPLE The following example illustrates the procedure to calculate the required AT-cut crystal frequency needed to generate a desired output frequency. Assuming the requirement to generate an output frequency of 622.08 MHz, Table 1 shows that the desired output frequency lies between 583.5 and 680 MHz. DESIRED OUTPUT FREQUENCY (MHz) From 650.0 583.5 510.0 (1) To 766.7 650.0 587.5 REQUIRED INPUT CRYSTAL FREQUENCY (MHz) From 32.500 29.174 31.875 To 38.333 32.500 36.719 VCO 2 VCO 1 VCO 2 1 1 1 3 3 4 20 20 16 VCO SELECTION OUTPUT DIVIDER PRESCALER SETTING FEEDBACK DIVIDER (1) The feedback divider is set automatically with respect to the prescaler setting. So this means that the device must be configured with: VCO = VCO 1 Output divider = 1 Prescaler setting = 3 To determine the right crystal frequency needed to get 622.08 MHz with these settings, substitute values into Equation 1. f xtal + OutputDivider FeedbackDivider f out f xtal + 1 20 622.08 + 31.154 MHz (2) The AT-cut frequency should be 31.154 MHz (between 29.174 MHz and 32.500 MHz. as shown in Table 1) . SERIAL INTERFACE AND CONTROL The CDCE421 uses a unique Texas Instruments proprietary interface protocol that can be configured and programmed via a single input pin to the device. The architecture enables only writing to the device from this input pin. Reading the content of a register can be achieved by sending a read command on the input pin and monitoring the output pins (LVDS or LVPECL). In a case where the output pins cannot be used to read the content, the software controlling the interface must account for what is written to the EEPROM and when it is programmed. Monitoring the outputs verifies the programming modes, and cycling power on the device verifies that the EEPROM is holding the proper configuration. The CDCE421 can be configured and programmed via the SDATA input pin. For this purpose, a square-wave programming sequence must be written to the device as described in the following section. During the EEPROM programming phase, the device requires a stable VCC of 3.3 V ± 100 mV for secure writing of the EEPROM cells. After each Write to WordX, the written data is latched, made effective, and offers look-ahead before the actual data is stored into the EEPROM. The following table summarizes all valid programming commands. SDATA 00 1100 11 1011 000 xxxx xxxx 100 xxxx xxxx 010 xxxx xxxx 110 xxxx xxxx FUNCTION Enter Programming Mode (State 1 → State 2); bits must be sent in the specified order with the specified timing. Otherwise, a time-out occurs. Enter Register Read Back Mode; bits must be sent in the specified order with the specified timing. Otherwise, a time-out occurs. Write to Word0 (State 2) (1) (2) (3) Write to Word1 (State 2)(1) (2) (3) Write to Word2 (State 2)(1) (2) (3) Write to Word3 (State 2)(1) (2) (3) (1) (2) (3) 4 Each rising edge causes a bit to be latched. Between the bits, some longer time delays can occur, but this has no effect on the data. A Write to WordX is expected to be 10 bits long. After the 10th bit, the respective word is latched and its effect can be observed as look-ahead function. Submit Documentation Feedback www.ti.com CDCE421 SCAS842 – APRIL 2007 SDATA 001 xxxx xxxx 101 xxxx xxxx 111 xxxx xxxx 111 0101 0101 111 1111 0000 111 0000 0000 Write to Word4 (State 2)(1) (2) (3) Write to Word5 (State 2)(1) (2) (3) FUNCTION State machine jump: All other patterns not defined as follows cause an exit to normal mode. Jump: Enter EEPROM programming with EEPROM lock (State 2 → State 3) Jump: Enter EEPROM programming wi