PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

CDC706 www.ti.com SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007 PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER FEATURES • • • • • High Performance 2:6 PLL Based Clock Synthesizer / Multiplier / Divider User Programmable PLL Frequencies Easy In-Circuit Programming via SMBus Data Interface Wide PLL Divider Ratio Allows 0-PPM Output Clock Error Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal Accepts Crystal Frequencies from 8 MHz up to 54 MHz Accepts LVCMOS or Differential Input Frequencies up to 200 MHz Two Programmable Control Inputs [S0/S1] for User Defined Control Signals Six LVCMOS Outputs with Output Frequencies up to 300 MHz LVCMOS Outputs can be Programmed for Complementary Signals Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output PLL Loop Filter Components Integrated Low Period Jitter (Typical 60 ps) Features Spread Spectrum Clocking (SSC) for Lowering System EMI Programmable Output Slew-Rate Control (SRC) for Lowering System EMI 3.3-V Device Power Supply Industrial Temperature Range –40°C to 85°C Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™) • • Packaged in 20-Pin TSSOP Factory Programmable for Customized Default Settings are Available. Contact TI Sales for More Details. APPLICATIONS • • • Wireless Base Stations Network Line Cards Datacom / Telecom TERMINAL ASSIGNMENT PW PACKAGE (TOP VIEW) • • • • • • S0/CLK_SEL S1 VCC GND CLK_IN0 CLK_IN1 VCC GND SDATA SCLOCK 1 2 3 4 TSSOP 20 5 Pitch 0,65 mm 6 6.6 x 6.6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Y5 Y4 VCCOUT2 GND Y3 Y2 VCCOUT1 GND Y1 Y0 • • • • • • • Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Pro-Clock is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated CDC706 www.ti.com SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The CDC706 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDC706 is very flexible. It has the capability to produce an almost independent output frequency from a given input frequency. The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller. To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output. The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27-MHz). The CDC706 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 300 MHz and optimized for zero-ppm applications with wide divider factors. PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise. Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL. The device provides customized applications. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration via the serial SMBus Interface. Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc). The CDC706 has three power supply pins, VCC, VCCOUT1, and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output current drive is limited. The CDC706 is characterized for operation from –40°C to 85°C. 2 Submit Documentation Feedback CDC706 www.ti.com SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007 FUNCTIONAL BLOCK DIAGRAM VCC PLL Bypass VCO1 Bypass PLL1 GND VCCOUT1 Output Switch Matrix prg. 9 Bit Divider M PFD Filter MUX 6 x Programmable 7-Bit Divider P0, P1, P2, P3, P4, P5, and Inversion Logic LV CMOS Y0 prg. 12 Bit Divider N VCO LV CMOS Y1 CLK_IN0 CLK_IN1 XO or 2 LVCMOS or Differential Input VCO2 Bypass prg. 9 Bit Divider M PFD Filter VCO SSC On/Off Crystal or Clock Input PLL2 w/ SSC 5 x 6 Programmable Switch A 6 x 6 Programmable Switch B LV CMOS Y2 MUX prg. 12 Bit Divider N LV CMOS Y3 SO/CLK_SEL PROGRAMMING S1 SDATA SCLOCK Factory Prg. LOGIC SMBUS LOGIC prg. 9 Bit Divider M VCO3 Bypass PLL3 LV CMOS Y4 PFD Filter MUX LV CMOS Y5 prg. 12 Bit Divider N VCO GND VCCOUT2 OUTPUT SWITCH MATRIX 5x6 − Switch A 7-Bit Divider P0 Input CLK (PLL Bypass) 6x6 − Switch B Y0 P1 Y1 PLL 1 P2 Y2 PLL 2 non SSC PLL 2 w/ SSC P3 Y3 P4 Y4 P5 PLL 3 Y5 Programming Submit Documentation Feedback 3 CDC706 www.ti.com SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007 TERMINAL FUNCTIONS TERMINAL NAME Y0 to Y5 CLK_IN0 CLK_IN1 VCC VCCOUT1 VCCOUT2 GND S0, CLK_SEL S1 SDATA SCLOCK TSSOP20 NO. 11, 12, 15, 16, 19, 20 5 6 3, 7 14 18 4, 8, 13, 17 1 2 9 10 I/O DESCRIPTION O I I/O Power Power Power Ground I I I/O I LVCMOS outputs Dependent on SMBus settings, CLK_IN0 is the crystal oscillator input and can also be used as LVCMOS input or as positive differential signal inputs. Dependent on SMBus settings, CLK_IN1 is serving as the crystal oscillator output or can be the second LVCMOS input or the negative differential signal input. 3.3-V power supply for the device. Power supply for outputs Y0, Y1. Power supply for outputs Y2, Y3, Y4, Y5. Ground User programmable control input S0 (PLL bypass or power-down mode) , or CLK_SEL (selects one of two LVCMOS clock inputs), dependent on the SMBus settings; LVCMOS inputs; internal pullup 150 kΩ. User programmable control input S1 (output enable/disable or all output low), dependent on the SMBus settings; LVCMOS inputs; internal pullup 150 kΩ Serial control data input/output for SMBus controller; LVCMOS input Serial control clock input for SMBus controller; LVCMOS input ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VCC VI VO II IO Tstg TJ (1) (2) Supply voltage range Input voltage range (2) Output voltage range (2) Input current (VI < 0, V I > VCC) Continuous output current Storage temperature range Maximum junction temperature (1) VALUE –0.5 to 4.6 –0.5 to VCC + 0.5 – 0.5 to VCC + 0.5 ±20 ±50 –65 to 150 125 UNIT V V V mA mA °C °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. PACKAGE THERMAL RESISTANCE for TSSOP20 (PW) Package (1) (2) PARAMETER AIRFLOW (LFM) 0 θJA Thermal resistance junction-to-ambient 150 250 500 θJC (1) (2) Thermal resistance junction-to-case °C/W 66.3 59.3 56.3 51.9 19.7 The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. 4 Submit Documentation Feedback CDC706 www.ti.com SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VCC VCCOUT1 VCCOUT2 VIL VIH VIthresh VI |VID| VIC IOH/IOL IOH/IOL CL TA Device supply voltage Output Y0, Y1 supply voltage Output Y2, Y3, Y4, Y5 supply voltage Low level input voltage LVCMOS High level input voltage LVCMOS Input voltage threshold LVCMOS Input voltage range LVCMOS Differential input voltage Common-mode for differential input voltage Output current (3.3 V) Output current (2.5 V) Output load LVCMOS Operating free-air temperature –40 0 0.1 0.2 Vcc - 0.6 ±6 ±4 25 85 0.7 VCC 0.5 VCC 3.6 3 2.3 2.3 NOM 3.3 MAX 3.6 3.6 3.6 0.3 VCC UNIT V V V V V V V V V mA mA pF °C RECOMMENDED CRYSTAL SPECIFICATIONS MIN fXtal ESR CIN (1) (2) Crystal input frequency range (fundamental mode) Effective series resistance (1) (2) Input capacitance CLK_IN0 and CLK_IN1 8 15 3 NOM 27 MAX 54 60 UNIT MHz Ω pF For crystal frequencies above 50 MHz the effective series resistor should not exceed 50