(CDC421xxx) CRYSTAL-OSCILLATOR CLOCK GENERATOR

CDC421xxx www.ti.com SLAS540 – APRIL 2007 FULLY INTEGRATED FIXED FREQUENCY LOW-JITTER, CRYSTAL-OSCILLATOR CLOCK GENERATOR FEATURES • • Single 3.3 V Supply High-Performance Clock Generator, Incorporating Crystal Oscillator Circuitry With Integrated Frequency Synthesizer Low Output Jitter, as Low as 380 fs (rms integrated between 10 kHz–20 MHz) Low Phase Noise at 312.5 MHz, Less Than –120 dBc/Hz at 10 kHz and –147 dBc/Hz at 10 MHz Offset From the Carrier Supports Crystal Frequencies or LVCMOS Input Frequencies at 31.25 MHz, 33.33 MHz, and 35.42 MHz A A A A • • • • • • • • • • • • Output Frequencies: 100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, and 312.5 MHz Differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) Output Fully Integrated Voltage-Controlled Oscillator (VCO) Running from 1.75 GHz to 2.35 GHz Typical Power Consumption 300 mW Chip-Enable Control Pin QFN-24 Package ESD Protection Exceeds 2 kV HBM Industrial Temperature Range –40°C to 85°C APPLICATIONS Low-Cost, Low-Jitter Frequency Multiplier External Crystal Loop Filter Crystal Oscillator Input PFD/Charge Pump CLK Output Divider Prescaler VCO Feedback Divider LVPECL NCLK B0216-02 DESCRIPTION CDC421xxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz–2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for the PLL-based frequency synthesizer. The output frequency (fout) is proportional to the frequency of the input crystal (fxtal). The device operates in a 3.3 V supply environment and is characterized for operation from –40°C to 85°C. CDC421xxx is available in a QFN-24 package. A high-level block diagram of the CDC421xxx is shown in Figure 1. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated CDC421xxx SLAS540 – APRIL 2007 www.ti.com XIN 1 XIN 2 Crystal Oscillator Loop Filter PFD/ Charge Pump VCO Prescaler Output Divider Feedback Divider B0230-01 Figure 1. High-Level Block Diagram of the CDC421xxx PACKAGE (QFN-24) The CDC421xxx is packaged in a QFN-24 terminal package. The QFN package footprint is shown. Terminal locations and numbers are shown in Figure 2. RGE PACKAGE (TOP VIEW) XIN 1 XIN2 NC NC NC 20 21 24 23 CE NC NC NC NC NC 22 19 NC 1 2 3 18 17 16 NC VCC VCC NC NC NC CDC421xxx 4 5 6 15 14 13 GND GND 10 NC 11 OUTN OUTP NC 12 7 8 9 P0024-06 Figure 2. Pinout of the CDC421xxx QFN-24 Package The terminal functions table shows the terminal descriptions for the CDC421xxx QFN-24 package. Table 1. TERMINAL FUNCTIONS TERMINAL NAME VCC GND XIN 1 XIN 2 NO. 16, 17 8, 9 21 22 TYPE Power GND I I ESD PROTECTION Y Y Y N 3.3V power supply Ground In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the other end of the crystal. In LVCMOS single-ended driven mode, XIN1 (pin 21) acts as input reference and XIN2 should connect to GND. DESCRIPTION 2 Submit Documentation Feedback www.ti.com CDC421xxx SLAS540 – APRIL 2007 Table 1. TERMINAL FUNCTIONS (continued) TERMINAL NAME CE OUTP OUTN NC NO. 1 10 7 2–6, 11–15, 18–20, 23, 24 TYPE ESD PROTECTION Y Y Y Y DESCRIPTION Chip enable (LVCMOS input) CE = 1 enables the device and the outputs. CE = 0 disables all current sources (LVPECLP = LVPECLN = Hi-Z). High-speed positive differential LVPECL output. (Outputs are enabled by CE ) High-speed negative differential LVPECL output. (Outputs are enabled by CE ) TI test pin. Do not connect; leave floating. I O O I or O DEVICE SELECTION The CDC421xxx device is an LVPECL low-phase-noise clock generator designed to work with a low-frequency AT-crystal oscillator of a single-ended LVCMOS. Table 2. Device Selection Table for CDC421xxx CDC421xxx DEVICE MARKING 421100 421100 421106 421106 421125 421125 421156 421156 421212 421212 421250 421250 421312 421312 ORDERING PART NUMBER CDC421100RGER CDC421100RGET CDC421106RGER CDC421106RGET CDC421125RGER CDC421125RGET CDC421156RGER CDC421156RGET CDC421212RGER CDC421212RGET CDC421250RGER CDC421250RGET CDC421312RGER CDC421312RGET PACKAGE QFN-24 tape and reel QFN-24 small tape and reel QFN-24 tape and reel QFN-24 small tape and reel QFN-24 tape and reel QFN-24 small tape and reel QFN-24 tape and reel QFN-24 small tape and reel QFN-24 tape and reel QFN-24 small tape and reel QFN-24 tape and reel QFN-24 small tape and reel QFN-24 tape and reel QFN-24 small tape and reel INPUT FREQUENCY OR CRYSTAL VALUE (MHz) 33.3333 33.3333 35.4167 35.4167 31.2500 31.2500 31.2500 31.2500 35.4167 35.4167 31.2500 31.2500 31.2500 31.2500 OUTPUT FREQUENCY FOR THE SPECIFIED INPUT FREQUENCY (MHz) 100.00 100.00 106.25 106.25 125.00 125.00 156.25 156.25 212.50 212.50 250.00 250.00 312.50 312.50 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE VCC VI IO TA TJ Tstg (1) (2) Supply voltage (2) Voltage range for all other input pins (2) Output current for LVPECL Electrostatic discharge (HBM) Characterized free-air temperature range (no airflow) Maximum junction temperature Storage temperature range –0.5 to 4.6 –0.5 to VCC + 0.5 –50 2k –40 to 85 125 –65 to 150 UNIT V V mA V °C °C °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Submit Documentation Feedback 3 CDC421xxx SLAS540 – APRIL 2007 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VCC TA Supply voltage Ambient temperature, no airflow, no heat sink 3 –40 NOM 3.3 MAX 3.6 85 UNIT V °C ELECTRICAL CHARACTERISTICS over recommended operating conditions for CDC421xxx device PARAMETER VCC IVCC fCLK VOH VOL |VOD| tr tf LVCMOS INPUT VIL,CMOS VIH,CMOS IL,CMOS IH,CMOS Low-level CMOS input voltage High-level CMOS input voltage Low-level CMOS input current High-level CMOS input current VCC = 3.3 V VCC = 3.3 V VCC = VCC max, VIL = 0 V VCC = VCC min, VIH = 3.7 V 0.7 VCC –200 200 0.3 VCC V V µA µA Supply voltage Total current at 3.3 V Output frequency LVPECL high-level output voltage LVPECL low-level output voltage LVPECL differential output voltage Output rise time Output fall time Duty cycle of the output waveform 20% to 80% of VOUTpp 80% to 20% of VOUTpp 45% 3.3 V, 312.5 MHz 100 VCC – 1.20 VCC – 2.17 407 170 170 55% TEST CONDITIONS MIN 3 TYP 3.3 91 MAX 3.6 110 312.5 VCC – 0.81 VCC – 1.36 1076 UNIT V mA MHz V V mV ps ps LVPECL OUTPUT 4 Submit Documentation Feedback www.ti.com CDC421xxx SLAS540 – APRIL 2007 JITTER CHARACTERISTICS IN INPUT CLOCK MODE The jitter characterization test is performed using an LVCMOS input signal driving the CDC421xxx device. 0.1 mF XIN 1 50 W 100 pF CDC421xxx XIN 2 Phase Noise Analyzer 150 W 150 W 150 W S0246-02 Figure 3. Jitter Test Configuration for an LVTTL Input Driving CDC421xxx For the cases of the CDC421xxx being referenced by an external, clean LVCMOS input of 31.25 MHz, 33.33 MHz and 35.4167 MHz, the following tables list the measured SSB phase noise of all the outputs supported by the CDC421xxx device, (100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, and 312.5 MHz) from 100 Hz to 20 MHz from the carrier. Table 3. Phase Noise Parameters With LVCMOS Input of 33.3333 MHz and LVPECL Output at 100.00 MHz PARAMETER Phase Noise Specifications Under Following Conditions: fin = 33.3333 MHz, fout = 100.00 MHz phn100 phn1K phn10k phn100k phn1M phn10M phn20M JRMS Tj Dj Phase noise at 100 Hz Phase noise at 1 kHz Phase noise at 10 kHz Phase noise at 100 kHz Phase Noise at 1 MHz Phase noise at 10 MHz Phase noise at 20 MHz RMS jitter integrated from 12 kHz to 20 MHz Total jitter Deterministic jitter –111 –121 –131 –133 –142 –149 –149 507 35.33 11.54 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz fs ps ps MIN TYP MAX UNIT Table 4. Phase Noise Parameters With LVCMOS Input of 35.4167 MHz and LVPECL Output at 106.25 MHz PARAMETER Phase Noise Specifications Under Following Conditions: fin= 35.4167 MHz , fout = 106.25 MHz phn100 phn1K phn10k phn100k phn1M phn10M phn20M JRMS Tj Dj Phase noise at 100 Hz Phase noise at 1 kHz Phase noise at 10 kHz Phase noise at 100 kHz Phase noise at 1 MHz Phase noise at 10 MHz Phase noise at 20 MHz RMS jitter integrated from 12 kHz to 20 MHz Total jitter Deterministic jitter –112 –121 –125 –129 –142 –151 –151 530 30.39 11 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz fs ps ps MIN TYP MAX UNIT Submit Documentation Feedback 5 CDC421xxx SLAS540 – APRIL 2007 www.ti.com Table 5. Phase Noise Parameters With LVCMOS Input of 31.2500 MHz and LVPECL Output at 125.00 MHz PARAMETER Phase Noise Specifications Under Following Conditions: fin = 31.2500 MHz, fout = 125.00 MHz phn100 phn1K phn10k phn100k phn1M phn10M phn20M JRMS Tj Dj Phase noise at 100 Hz Phase noise at 1 kHz Phase noise at 10 kHz Phase noise at 100 kHz Phase noise at 1 MHz Phase noise at 10 MHz Phase noise at 20 MHz RMS jitter integrated from 12 kHz to 20 MHz Total jitter Deterministic jitt