High Speed CMOS Logic Analog Multiplexers/Demultiplexers

Data sheet acquired from Harris Semiconductor SCHS122A CD54HC4051, CD74HC4051, CD74HCT4051, CD74HC4052, CD74HCT4052, CD74HC4053, CD74HCT4053 High Speed CMOS Logic Analog Multiplexers/Demultiplexers Description These devices are digitally controlled analog switches which utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. These analog multiplexers/demultiplexers control analog voltages that may vary across the voltage supply range (i.e. VCC to VEE). They are bidirectional switches thus allowing any analog input to be used as an output and visa-versa. The switches have low “on” resistance and low “off” leakages. In addition, all three devices have an enable control which, when high, disables all switches to their “off” state. November 1997 - Revised April 1999 Features [ /Title (CD54 HC405 1, CD74 HC405 1, CD74 HCT40 51, CD74 HC405 2, • Wide Analog Input Voltage Range . . . . . . . . . . ±5V Max • Low “On” Resistance - 70Ω Typical (VCC - VEE = 4.5V) - 40Ω Typical (VCC - VEE = 9V) • Low Crosstalk between Switches • Fast Switching and Propagation Speeds • “Break-Before-Make” Switching • Wide Operating Temperature Range . . -55oC to 125oC • CD54HC/CD74HC Types - Operation Control Voltage . . . . . . . . . . . . . . 2V to 6V - Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V - High Noise Immunity . . . NIL = 30%, NIH = 30% of VCC, VCC = 5V • CD54HCT/CD74HCT Types - Operation Control Voltage . . . . . . . . . . . 4.5V to 5.5V - Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V - Direct LSTTL Input Logic Compatibility . . . VIL = 0.8V Max, VIH = 2V Min - CMOS Input Compatibility . . . . . II ≤ 1µA at VOL, VOH Ordering Information PART NUMBER CD54HC4051F CD74HC4051E CD74HC4052E CD74HC4053E CD74HCT4051E CD74HCT4052E CD74HCT4053E CD74HC4051M CD74HC4052M CD74HC4053M CD74HCT4051M CD74HCT4052M CD74HCT4053M CD74HCT4053PW CD74HCT4052SM NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. For the TSSOP package only, add the suffix R to obtain the variant in the tape and reel. 2. Wafer or die is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld PDIP 16 Ld PDIP 16 Ld PDIP 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld TSSOP 16 Ld SSOP M16.15A PKG. NO. F16.3 E16.3 E16.3 E16.3 E16.3 E16.3 E16.3 M16.15 M16.15 M16.15 M16.15 M16.15 M16.15 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 File Number 1676.1 1 CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53 Pinouts CD54HC4051 CD74HC4051, CD74HCT4051 (CERDIP, PDIP, SOIC) TOP VIEW CHANNEL IN/OUT COM OUT/IN CHANNEL IN/OUT A4 1 A6 2 A 3 A7 4 A5 5 E 6 VEE 7 GND 8 16 VCC 15 A2 14 A1 13 A0 12 A3 11 S0 10 S1 9 S2 ADDRESS SELECT CHANNEL IN/OUT CHANNEL IN/OUT CD74HC4052, CD74HCT4052 (PDIP, SOIC) TOP VIEW B0 1 B2 2 16 VCC 15 A2 14 A1 13 AN 12 A0 11 A3 10 S0 9 S1 CHANNEL IN/OUT COM OUT/IN CHANNEL IN/OUT COM OUT/IN BN 3 CHANNEL IN/OUT B3 4 B1 5 E 6 VEE 7 GND 8 CD74HC4053, CD74HCT4053 (PDIP, SOIC, TSSOP) TOP VIEW B1 1 CHANNEL IN/OUT B0 2 C1 3 COM OUT/IN CN 4 IN/OUT C0 5 E 6 VEE 7 GND 8 16 VCC 15 BN 14 AN 13 A1 12 A0 11 S0 10 S1 9 S2 COM OUT/IN COM OUT/IN CHANNEL IN/OUT 2 CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53 Functional Diagram of HC/HCT4051 CHANNEL IN/OUT VCC 16 A7 4 A6 2 A5 5 A4 1 A3 12 A2 15 A1 14 A0 13 TG TG S0 11 TG S1 10 LOGIC LEVEL CONVERSION BINARY TO 1 OF 8 DECODER WITH ENABLE TG 3 TG A COMMON OUT/IN S2 9 TG TG E 6 TG 8 GND 7 VEE TRUTH TABLE CD54/74HC/HCT4051 INPUT STATES ENABLE L L L L L L L L H X = Don’t care S2 L L L L H H H H X S1 L L H H L L H H X S0 L H L H L H L H X “ON” CHANNELS A0 A1 A2 A3 A4 A5 A6 A7 None 3 CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53 Functional Diagram of HC/HCT4052 A CHANNELS IN/OUT A3 VCC 16 TG 11 A2 15 A1 14 A0 12 TG TG S1 9 LOGIC LEVEL CONVERSION BINARY TO 1 OF 4 DECODER WITH ENABLE TG 13 COMMON A OUT/IN COMMON B OUT/IN TG 3 S0 10 TG E 6 TG TG 8 GND 7 VEE 1 B0 5 B1 2 B2 4 B3 B CHANNELS IN/OUT TRUTH TABLE CD74HC4052, CD74HCT4052 INPUT STATES ENABLE L L L L H X = Don’t care S1 L L H H X S0 L H L H X “ON” CHANNELS A0, B0 A1, B1 A2. B2 A3, B3 None 4 CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53 Functional Diagram of HC/HCT4053 VCC LOGIC LEVEL CONVERSION 16 BINARY TO 1 OF 2 DECODERS WITH ENABLE IN/OUT C1 3 C0 5 B1 1 B0 2 A1 13 A0 12 TG 14 A COMMON OUT/IN S0 11 TG TG S1 10 TG 15 B COMMON OUT/IN S2 9 TG 4 TG C COMMON OUT/IN E 6 8 GND 7 VEE TRUTH TABLE CD74HC4053, CD74HCT4053 INPUT STATES ENABLE L L L L L L L L H X = Don’t care S0 L H L H L H L H X S1 L L H H L L H H X S2 L L L L H H H H X “ON” CHANNELS C0, B0, A0 C0, B0, A1 C0, B1, A0 C0, B1, A1 C1, B0, A0 C1, B0, A1 C1, B1, A0 C1, B1, A1 None 5 CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53 Absolute Maximum Ratings (Note 3) DC Supply Voltage, VCC - VEE . . . . . . . . . . . . . . . . . -0.5V to 10.5V DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V DC Supply Voltage, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.5V to -7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Switch Diode Current, IOK For VI < VEE -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . .±20mA DC Switch Current, (Note 2) For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA DC VEE Current, IEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20mA Thermal Information Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A CERDIP Package . . . . . . . . . . . . . . . . 130 55 TSSOP Package . . . . . . . . . . . . . . . . . 149 35 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Recommended Operating Conditions PARAMETER For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges MIN MAX UNITS Supply Voltage Range (For TA = Full Package Temperature Range), VCC (Note 5) CD54/74HC Types CD54/74HCT Types Supply Voltage Range (For TA = Full Package Temperature Range), VCC - VEE CD54/74HC Types, CD54/74HCT Types (See Figure 1) Supply Voltage Range (For TA = Full Package Temperature Range), VEE (Note 5) CD54/74HC Types, CD54/74HCT Types (See Figure 2) DC Input Control Voltage, VI Analog Switch I/O Voltage, VIS Operating Temperature, TA Input Rise and Fall Times, tr, tf 2V 4.5V 6V 0 0 0 1000 500 400 ns ns ns 0 GND VEE -55 -6 VCC VCC 125 V V V oC 2 4.5 6 5.5 V V 2 10 V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. All voltages referenced to GND unless otherwise specified. 4. θJA is measured with the component mounted on an evaluation PC board in free air. 5. In certain applications, the external load resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6V (calculated from rON values shown in Electrical Specifications table). No VCC current will flow through RL if the switch current flows into terminal 3 on the HC/HCT4051; terminals 3 and 13 on the HC/HCT4052; terminals 4, 14 and 15 on the HC/HCT4053. Recommended Operating Area as a Function of Supply Voltages 8 VCC - GND (V) 6 HCT 4 2 0 0 2 4 6 8 10 12 HC VCC - GND (V) 8 6 HCT 4 2 0 0 -2 -4 -6 -8 HC VCC - VEE (V) VEE - GND (V) FIGURE 1. FIGURE 2. 6 CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53 DC Electrical Specifications TEST CONDITIONS VIS (V) VI (V) VEE (V) VCC (V) AMBIENT TEMPERATURE, TA 25oC MIN TYP MAX -40oC - 85oC MIN MAX -55oC - 125oC MIN MAX UNITS PARAMETER HC TYPES High Level Input Voltage, VIH 2 4.5 6 1.5 3.15 4.2 - 70 60 40 90 80 45 10 8.5 5 0.5 1.35 1.8 160 140 120 180 160 130 - 1.5 3.15 4.2 - 0.5 1.35 1.8 200 175 150 225 200 162 - 1.5 3.15 4.2 - 0 0.5 1.35 1.8 240 210 180 270 240 195 - V V V V V V Ω Ω Ω Ω Ω Ω Ω Ω Ω Low Level Input Voltage, VIL 2 4.5 6 On Resistance, rON IO = 1mA, (Figure 11) VCC or VEE VIL or VIH 0 0 -4.5 4.5 6 4.5 4.5 6 4.5 4.5 6 4.5 VCC to VEE 0 0 -4.5 Maximum On Resistance Between any Two Channels, ∆rON Switch On/Off Leakage Current, IIZ 1 and 2 Channels 4053 4 Channels 4052 8 Channels 4051 Control Input Leakage Current, IIL Quiescent Device Current, ICC IO = 0 When VIS = VEE, VOS = VCC When VIS = VCC, VOS = VEE VCC or GND VCC or GND For Switch Off: When VIS = VCC, VOS = VEE; When VIS = VEE, VOS = VCC For Switch On: All Applicable Combinations of VIS and VOS Voltage Levels VIL or VIH 0 0 -4.5 0 -5 0 -5 0 -5 0 0 -5 6 5 6 5 6 5 6 6 5 - - ±0.1 ±0.1 ±0.1 ±0.2 ±0.2 ±0.4 ±0.1 8 16 - ±1 ±1 ±1 ±2 ±2 ±4 ±1 80 160 - ±1 ±1 ±1 ±2 ±2 ±4 ±1 160