High-Speed CMOS Logic Quad Buffer

CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 Data sheet acquired from Harris Semiconductor SCHS143C November 1997 - Revised August 2003 High-Speed CMOS Logic Quad Buffer, Three-State Description The ’HC125 and ’HCT125 contain 4 independent three-state buffers, each having its own output enable input, which when “HIGH” puts the output in the high impedance state. Features • Three-State Outputs [ /Title (CD74 HC125 , CD74 HCT12 5) /Subject (High Speed CMOS Logic Quad Buffer, ThreeState) • Separate Output Enable Inputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Ordering Information PART NUMBER CD54HC125F3A CD54HCT125F3A CD74HC125E CD74HC125M CD74HC125MT CD74HC125M96 CD74HCT125E CD74HCT125M TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC www.DataSheet4U.com CD74HCT125MT CD74HCT125M96 NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC125, CD54HCT125 (CERDIP) CD74HC125, CD74HCT125 (PDIP, SOIC) TOP VIEW 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 Functional Diagram 1OE 1A 2OE 2A 10 3OE 9 3A 13 4OE 12 4A 11 4Y GND = 7 VCC = 14 8 3Y 1 2 4 5 6 3 1Y 2Y TRUTH TABLE INPUTS nA H L X H= High Voltage Level L= Low Voltage Level X= Don’t Care Z= High Impedance, OFF State nOE L L H OUTPUTS nY H L Z Logic Diagram P nA n nOE nY 2 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . ±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 -0.02 -0.02 High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL -6 -7.8 0.02 0.02 0.02 Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND 6 7.8 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 V V V V V V V V V V V V V V V V µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS 3 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Quiescent Device Current Three-State Leakage Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load Three-State Leakage Current NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ∆ICC (Note 2) IOZ VCC to GND VCC or GND VCC -2.1 VIL or VIH VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC IOZ VI (V) VCC or GND VIL or VIH IO (mA) VCC (V) 0 6 6 MIN 25oC TYP MAX 8 ±0.5 -40oC TO 85oC MIN MAX 80 ±5 -55oC TO 125oC MIN MAX 160 ±10 UNITS µA µA -6 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V 0 0 - 5.5 5.5 4.5 to 5.5 5.5 - 100 ±0.1 8 360 - ±1 80 450 - ±1 160 490 µA µA µA - - - ±0.5 - ±5 - ±10 µA HCT Input Loading Table INPUT nA, nOE UNIT LOADS 1 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 4 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 Switching Specifications Input tr, tf = 6ns TEST CONDITIONS 25oC VCC (V) TYP MAX -40oC TO 85oC -55oC TO 125oC MAX MAX UNITS PARAMETER HC TYPES Propagation Delay Time nA to nY SYMBOL tPLH, tPHL CL = 50pF 2 4.5 8 10 10 29 100 20 17 125 25 21 125 25 21 60 12 10 10 20 - 125 25 21 155 31 26 155 31 26 75 15 13 10 20 - 150 30 26 190 38 32 190 38 32 90 18 15 10 20 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF CL = 15pF CL = 50pF Enable Delay Time tPZL, tPZH CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Disable Delay Time tPLZ, tPHZ CL = 50pF CL = 50pF CL = 15pF CL = 50pF Output Transition Time tTLH, tTHL CL = 50pF 5 6 2 4.5 5 6 2 4.5 6 Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay Time nA to nY Output Enable Time CI CO CPD - 5 tPLH, tPHL CL = 50pF CL = 15pF 4.5 5 4.5 5 4.5 5 4.5 5 10 10 11 34 25 25 28 12 10 20 - 31 31 35 15 10 20 - 38 38 42 18 10 20 - ns ns ns ns ns ns ns pF pF pF tPZL, tPZH CL = 50pF CL = 15pF Output Disabling Time tPLZ, tPHZ CL = 50pF CL = 15pF Output Transition Times Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 3, 4) NOTES: tTLH, tTHL CI CO CPD CL = 50pF - 3. CPD is used to determine the dynamic power consumption, per channel. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 5 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 Test Circuits and Waveforms tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V GND tTHL INVERTING OUTPUT FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns OUTPUT DISABLE 90% 50% 10% tPZL 50% 10% tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 50% OUTPUTS DISABLED OUTPUTS ENABLED tPZH 6ns VCC GND FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tr OUTPUT DISABLE 6ns tf 2.7 1.3 tPLZ OUTPUT LOW TO OFF tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 6ns 3V 0.3 tPZL GND tPLZ OUTPUT LOW TO OFF 10% tPZH 1.3V 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 6 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device CD54HC125F CD54HC125F3A CD54HCT125F3A CD74HC125E CD74HC125EE4 CD74HC125M CD74HC125M96 CD74HC125M96E4 CD74HC125ME4 CD74HC125MT CD74HC125MTE4 CD74HCT125E CD74HCT125EE4 CD74HCT125M CD74HCT125M96 CD74HCT125M96E4 CD74HCT125ME4 CD74HCT125MT CD74HCT125MTE4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type CDIP CDIP