Memory ICs
BR24L02-W / BR24L02F-W / BR24L02FJ-W / BR24L02FV-W / BR24L02FVM-W
256×8 bit electrically erasable PROM
BR24L02-W / BR24L02F-W / BR24L02FJ-W BR24L02FV-W / BR24L02FVM-W
The BR24L02-W series is 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable.
∗ I2C BUS is a registered trademark of Philips.
Applications General purpose Features 1) 256 registers × 8 bits serial architecture. 2) Single power supply (1.8V to 5.5V). 3) Two wire serial interface. 4) Self-timed write cycle with automatic erase. 5) 8 byte page write mode. 6) Low power consumption. Write (5V) : 1.2mA (Typ.) Read (5V) : 0.2mA (Typ.) Standby (5V) : 0.1µA (Typ.) 7) DATA security Write protect feature (WP pin) . Inhibit to WRITE at low VCC. 8) Small package - - - DIP8 / SOP8 / SOP-J8 / SSOP-B8 / MSOP-8 9) High reliability EEPROM with Double-Cell structure 10) High reliability fine pattern CMOS technology. 11) Endurance : 1,000,000 erase / write cycles 12) Data retention : 40 years 13) Filtered inputs in SCL•SDA for noise suppression. 14) Initial data FFh in all address. Absolute maximum ratings (Ta=25°C)
Parameter Supply voltage Symbol VCC Limits −0.3 to +6.5 800 (DIP8) 450 (SOP8) Power dissipation Pd 450 (SOP-J8)
∗1 ∗2 ∗3
Unit V
mW
300 (SSOP-B8) ∗4 310 (MSOP8) Storage temperature Operating temperature Terminal voltage
∗1 ∗2, 3 ∗4 ∗5
∗5
Tstg Topr −
−65 to +125 −40 to +85 −0.3 to VCC+0.3
°C °C
V
Degradation is done at 8.0mW/°C for operation above 25°C. Degradation is done at 4.5mW/°C for operation above 25°C. Degradation is done at 3.0mW/°C for operation above 25°C. Degradation is done at 3.1mW/°C for operation above 25°C.
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Memory ICs
BR24L02-W / BR24L02F-W / BR24L02FJ-W / BR24L02FV-W / BR24L02FVM-W
Symbol VCC VIN Limits 1.8 to 5.5 0 to VCC Unit V V
Recommended operating conditions
Parameter Supply voltage Input voltage
DC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC=1.8 to 5.5V)
Parameter "HIGH" input volatge 1 "LOW" input volatge 1 "HIGH" input volatge 2 "LOW" input volatge 2 "LOW" output volatge 1 "LOW" output volatge 2 Input leakage current Output leakage current Symbol VIH1 VIL1 VIH2 VIL2 VOL1 VOL2 ILI ILO ICC1 Operating current ICC2 Standby current ISB − − − − 0.5 2.0 mA µA Min. 0.7VCC − 0.8VCC − − − −1 −1 − Typ. − − − − − − − − − Max. − 0.3VCC − 0.2VCC 0.4 0.2 1 1 2.0 Unit V V V V V V µA µA mA Conditions 2.5V≤VCC≤5.5V 2.5V≤VCC≤5.5V 1.8V≤VCC≤2.5V 1.8V≤VCC≤2.5V IOL=3.0mA, 2.5V≤VCC≤5.5V, (SDA) IOL=0.7mA, 1.8V≤VCC≤5.5V, (SDA) VIN=0V to VCC VOUT=0V to VCC VCC=5.5V, fSCL=400kHz, tWR=5ms, Byte Write, Page Write VCC=5.5V, fSCL=400kHz Random Read, Current Read, Sequential Read VCC=5.5V, SDA·SCL=VCC, A0, A1, A2=GND, WP=GND
This product is not designed for protection against radioactive rays.
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Memory ICs
Dimension
9.3±0.3 8 5
6.5±0.3
BR24L02-W / BR24L02F-W / BR24L02FJ-W / BR24L02FV-W / BR24L02FVM-W
5.0±0.2
8 5
1
0.51Min.
4 7.62
6.2±0.3 4.4±0.2
1
4
1.5±0.1 0.11
3.4±0.3
0.15±0.1 0.1
3.2±0.2
0.3±0.1
2.54 0.5±0.1 0° ~ 15°
1.27 0.4±0.1
Fig.1(a) PHYSICAL DIMENSION (Units : mm) DIP8 (BR24L02-W)
Fig.1(b) PHYSICAL DIMENSION (Units : mm) SOP8 (BR24L02F-W)
4.9±0.2
0.45Min. 6.0±0.3 3.9±0.2
6.4±0.3 4.4±0.2
8 7 6 5
3.0±0.2
8 5
1
4
1.375±0.1 0.175
1.15±0.1 0.1
1 2 3 4
0.15±0.1 0.1
0.2±0.1 0.1
1.27 0.42±0.1
0.22±0.1 0.65
(0.52)
Fig.1(c) PHYSICAL DIMENSION (Units : mm) SOP-J8 (BR24L02FJ-W)
Fig.1(d) PHYSICAL DIMENSION (Units : mm) SSOP-B8 (BR24L02FV-W)
2.9±0.1
8 5
4.0±0.2
2.8±0.1
1
4
0.475
0.9Max. 0.75±0.05 0.08±0.05
0.22−0.04 0.65 0.08 S
+0.05
0.29±0.15 0.6±0.2
+0.05 0.145−0.03
0.08 M
Fig.1(e) PHYSICAL DIMENSION (Units : mm) MSOP8 (BR24L02FVM-W)
0.3Min.
0.3Min.
3/25
Memory ICs
Block diagram
A0
BR24L02-W / BR24L02F-W / BR24L02FJ-W / BR24L02FV-W / BR24L02FVM-W
1
8bit
2kbit EEPROM array 8bit 8bits Slave word address register
STOP
8
VCC
A1
2
Address decoder
Data register
7
WP
A2
3
START
Control logic ACK
6
SCL
GND
4
High voltage generator
Vcc level detect
5
SDA
Fig.2 BLOCK DIAGRAM
Pin configuration
VCC
WP
SCL
SDA
8
7
6
5
BR24L02-W BR24L02F-W BR24L02FJ-W BR24L02FV-W BR24L02FVM-W
1
A0
2
A1
3
A2
4
GND
Fig.3 PIN LAYOUT
Pin name
Pin name
VCC GND A0, A1, A2 SCL SDA
I/O − − IN IN IN / OUT IN
Power supply Ground (0V)
Function
Slave address set Serial clock input Slave and word address, serial data input, serial data output Write protect input
∗1
WP
∗1 An open drain output requires a pull-up resistor.
4/25
Memory ICs
BR24L02-W / BR24L02F-W / BR24L02FJ-W / BR24L02FV-W / BR24L02FVM-W
Fast-mode 2.5V ≤ Vcc ≤ 5.5V Min. Typ. − − − − − − − − − − − − − − − − − − Max. 400 − − 0.3 0.3 − − − − 0.9 − − − 5 0.1 − − − − 0.6 1.2 − − 0.6 0.6 0 100 0.1 0.1 0.6 1.2 − − 0 0.1 1.0 Standard-mode 1.8V ≤ Vcc ≤ 5.5V Min. − 4.0 4.7 − − 4.0 4.7 0 250 0.2 0.2 4.7 4.7 − − 0 0.1 1.0 Typ. − − − − − − − − − − − − − − − − − − Max. 100 − − 1.0 0.3 − − − − 3.5 − − − 5 0.1 − − − kHz µs µs µs µs µs µs ns ns µs µs µs µs ms µs ns µs µs
AC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC=1.8 to 5.5V)
Parameter Clock frequency Data clock "HIGH" period Data clock "LOW" period SDA and SCL rise time SDA and SCL fall time Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup time Bus free time Write cycle time Noise spike width (SDA and SCL) WP hold time WP setup time WP high period
∗1 Not 100% tested. ∗1 ∗1
Symbol fSCL tHIGH tLOW tR tF
Unit
tHD:STA tSU:STA tHD:DAT tSU:DAT
tPD
tDH tSU:STO
tBUF tWR tl
tHD:WP tSU:WP tHIGH:WP
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Memory ICs
Synchronous data timing
BR24L02-W / BR24L02F-W / BR24L02FJ-W / BR24L02FV-W / BR24L02FVM-W
tR tF tHIGH
SCL tHD : STA SDA (IN) tBUF SDA (OUT) tPD tDH tSU : DAT tLOW tHD : DAT
SCL tSU : STA SDA tHD : STA tSU : STO
START BIT
STOP BIT
Fig.4 SYNCHRONOUS DATA TIMING
•SDA data is latched into the chip at the rising edge of SCL clock. •Output data toggles at the falling edge of SCL clock.
Write cycle timing
SCL
SDA
D0
WRITE DATA (n)
ACK tWR
STOP CONDITION START CONDITION
Fig.5 WRITE CYCLE TIMING
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Memory ICs
WP timing
BR24L02-W / BR24L02F-W / BR24L02FJ-W / BR24L02FV-W / BR24L02FVM-W
SCL
DATA (1) D1
DATA (n)
SDA
D0
ACK
ACK tWR STOP BIT
WP
tSU : WP
tHD : WP
Fig.6(a) WP TIMING OF THE WRITE OPERATION
SCL
DATA (1) D1
DATA (n)
SDA
D0
ACK
ACK
tHIGH : WP
WP
Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION
•For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in D0 of first byte until the end of tWR. ( See Fig.6 (a) ) During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) ) •In the case of setting WP “HIGH” during tWR, WRITE operation is stopped in the middle and the data of accessing address is not guaranteed. Please write correct data again in the case.
7/25
Memory ICs
BR24L02-W / BR24L02F-W / BR24L02FJ-W / BR24L02FV-W / BR24L02FVM-W
Device operation 1) Start condition (Recognition of start bit) • All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. • The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. (See Fig.4 SYNCHRONOUS DATA TIMING) 2) Stop condition (Recognition of stop bit) • All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. (See Fig.4 SYNCHRONOUS DATA TIMING) 3) Notice about write command • In the case that stop condition is not executed in WRITE mode, transferred data will not be written in a memory. 4) Device addressing • Following a START condition, the master output the slave address to be accessed. • The most significant four bits of the slave address are the “device type identifier”, for this device it is fixed as “1010”. • The next three bit (device address) identify the specified device on the bus. The device address is defined by the state of A0, A1 and A2 input pins. This IC works only when the device address inputted from SDA pin correspond to the state of A0, A1 and A2 input pins. Using this address scheme, up to eight device may be connected to the bus. The last bit of the stream (R/W - - - READ / WRITE) determines the operation to the performed. • The last bit of the stream (R/W - - - READ / WRITE) determines the operation to be performed. When set to “1”, a read operation is selected ; when set to “0”, a write operation is selected. R / W set to “0” - - - - - - WRITE (including word address input of Random Read) R / W set to “1” - - - - - - READ
1010
A2
A1
A0
R/W
5) Write protect (WP) When WP pin set to VCC (H level), write protect is set for 256 words (all address). When WP pin set to GND (L level), enable to write 256 words (all address). Either control this pin or connect to GND (or VCC). It is inhibited from being left unconnected.
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Memory ICs
BR24L02-W / BR24L02F-W / BR24L02FJ-W / BR24L02FV-W / BR24L02FVM-W
6) Acknowledge • Acknowledge is a software convention used to indicate successful data transfers. The transmitter device will release the bus after transmitting eight bits. (When inputting the slave address in the write or read operation, transmitter is µ-COM. When outputting the data in the read operation, it is this device.) • During the ninth clock cycle, the receiver will pull the SDA line LOW to Acknowledge that the eight bits of data has been received. (When inputting the slave address in the write or re
