Power amplifier

www.DataSheet4U.com BGY288 Power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 and PCS1900 Rev. 01 — 2 February 2005 Preliminary data sheet 1. Product profile 1.1 General description The BGY288 is a power amplifier module in a SOT775 surface mounted package with a plastic cap. In the module, a mix of state of the art technologies as InGaP, Si-Bicmos and Si passive integration are used to combine high performance with a small size. The module comprises two functional sections, one for low-band (GSM850/EGSM900) and one for high-band (DCS1800/PCS1900) with internal power detection, power control loop, input and output matching; see Figure 2. The power control circuit ensures a stable RF power output which is set by the voltage level on pin PC. The power control circuit is stabilized to compensate for variations in supply voltage, input power and temperature, and has a control range fully compliant with European Telecommunication Standards Institute (ETSI) time mask and power spectrum requirements. 1.2 Features 1.2.1 General features s Quad band GSM amplifier s 34 dBm controlled output power for GSM850/EGSM900 s Suited for GPRS class 12 (duty cycle δ = 4 : 8) s Integrated power control loop s 3.6 V nominal supply voltage s Very small size (8 mm × 8 mm) s 32.5 dBm controlled output power for DCS1800/PCS1900 s Easy on/off and band select by digital control voltage s Internal input and output matching s Specification based on 3GPP TS 45.005 1.2.2 RF performance RF performance with a typical pulsed, controlled output power at Tmb = 25 °C; VBAT = 3.6 V; VSTAB = 2.8 V; ZS = ZL = 50 Ω; PD(LB) = 2 dBm / PD(HB) = 0 dBm; δ = 2 : 8. s f = 824 MHz to 849 MHz; η @ PSAT = 50 %; PL = 34 dBm s f = 880 MHz to 915 MHz; η @ PSAT = 55 %; PL = 34 dBm s f = 1710 MHz to 1785 MHz; η @ PSAT = 50 %; PL = 32.5 dBm s f = 1850 MHz to 1910 MHz; η @ PSAT = 50 %; PL = 32.5 dBm 1.3 Applications s Digital cellular radio systems with Time Division Multiple Access (TDMA) operation (GSM systems) in four frequency bands: 824 MHz to 849 MHz, 880 MHz to 915 MHz, 1710 MHz to 1785 MHz and 1850 MHz to 1910 MHz. www.DataSheet4U.com Philips Semiconductors BGY288 Power amplifier with integrated control loop 2. Pinning information 2.1 Pinning RFO_HB RFO_LB 14 GND 1 16 15 GND 13 GND VBAT 2 12 VBAT VBAT 3 11 VBAT RFI_HB 4 10 RFI_LB TXON 5 6 PC 7 VSTAB 8 BAND 9 n.c. 001aac028 Transparent top view Fig 1. Pin configuration 2.2 Pin description Table 1: Symbol GND VBAT [1] Pin description Pin 1, 13, 15 2, 3 11, 12 4 5 6 7 8 9 10 14 16 inner pads analog input analog output analog output ground Type ground supply supply analog input logic input analog input supply logic input Description ground battery supply voltage for DCS1800/PCS1900 section battery supply voltage for GSM850/EGSM900 section DCS1800/PCS1900 transmit RF input RF power control enable input RF power control input stabilized supply voltage Low-Band (LB) (GSM850/EGSM900) or High-Band (HB) (DCS1800/PCS1900) select input not connected GSM850/EGSM900 transmit RF input GSM850/EGSM900 transmit RF output DCS1800/PCS1900 transmit RF output ground RFI_HB TXON PC VSTAB BAND n.c. RFI_LB RFO_LB RFO_HB [1] Pins 2, 3, 11 and 12 (VBAT) are not internally connected and must all be connected to the battery supply voltage. 9397 750 14011 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 01 — 2 February 2005 2 of 22 www.DataSheet4U.com Philips Semiconductors BGY288 Power amplifier with integrated control loop 3. Ordering information Table 2: Ordering information Package Name BGY288 Description leadless surface mounted package; plastic cap; 16 terminations Version SOT775A Type number 4. Block diagram 850 MHz and 900 MHz POWER AMPLIFIER RFI_LB 10 OUTPUT MATCHING 14 RFO_LB BIASING POWER SENSE POWER CONTROLLER 6 PC VSTAB TXON 7 5 (1) (1) LOGIC CONTROL BGY288 BAND 8 POWER SENSE BIASING RFI_HB 4 OUTPUT MATCHING 1800 MHz and 1900 MHz POWER AMPLIFIER 16 RFO_HB 001aab846 (1) Pull-down resistor. Fig 2. Block diagram 9397 750 14011 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 01 — 2 February 2005 3 of 22 www.DataSheet4U.com Philips Semiconductors BGY288 Power amplifier with integrated control loop 5. Functional description 5.1 Operating conditions The BGY288 is designed to meet the 3GPP TS 45.005 technical specification for the ETSI. 5.2 Power amplifier The low band (GSM850 and EGSM900) and the high band (DCS1800 and PCS1900) channel power amplifiers each comprises three cascaded gain stages, input and output matching and harmonic filters. The output power of each amplifier is determined by the bias on each of its 3 gain stages and is controlled by an internal signal generated in the power controller block. Each power amplifier block generates a power sense signal which is routed internally to the power control block. 5.3 Control logic The control logic block generates the various signals to control the complete BGY288 depending on the signal levels on pins TXON and BAND, as indicated in Table 3. The control logic block supply voltage is via pin VSTAB. When pin VSTAB = 0 V, the BGY288 is in Idle mode and the battery current consumption is almost zero. The power control block is enabled when pin TXON goes HIGH. The low band (GSM850/EGSM900) channel is enabled when pin BAND goes LOW and the high band (DCS1800/PCS1900) channel is enabled when pin BAND goes HIGH. Both TXON and BAND inputs have pull-down resistors of approximately 1 MΩ. 5.4 Power controller The main inputs to the power controller block are the RF power control signal via pin PC and the output power sense signal internally generated by each power amplifier block. The PC signal is the reference voltage for the requested level of output power, and is usually generated by an external digital-to-analog converter. The PC signal is buffered and compared with the output power sense signal. The resultant error signal is then amplified by one of two integrators, the selection of which being dependant on the level of the BAND signal. The output of the selected integrator is the internal signal which controls the biasing circuits of the selected channel. 5.5 Mode control Table 3: Mode Idle Mode control Mode description VSTAB (V) TXON LOW BAND LOW HIGH or LOW LOW HIGH PC (V) < 0.15 < 0.15 < 2.5 < 2.5 power amplifier fully off; minimal leakage current 0 Standby control logic functioning; power amplifier off LB TX HB TX low-band transmit mode (GSM850/EGSM900) high-band transmit mode (DCS1800/PCS1900) 2.6 to 3 LOW 2.6 to 3 HIGH 2.6 to 3 HIGH 9397 750 14011 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 01 — 2 February 2005 4 of 22 www.DataSheet4U.com Philips Semiconductors BGY288 Power amplifier with integrated control loop 6. Timing dB PL(LB), PL(HB) +4 +1 −1 −6 (**) −30 (***) (*) (147 bits) 10 µs 8 µs 10 µs 7056/13 (542.8) µs 10 µs 8 µs 10 µs t VSTAB td1 TXON td4 BAND td2 PD(LB), PD(HB) td3 PC td8 td7 td5 td6 td9 001aab847 Fig 3. Timing diagram Table 4: Timing characteristics ZS = ZL = 50 Ω; PD(LB) = 0 dBm to 4 dBm / PD(HB) = −2 dBm to +2 dBm; VBAT = 3.1 V to 4.6 V; VSTAB = 2.6 V to 3.0 V; Tmb = −20 °C to 85 °C; δ = 1 : 8 to 4 : 8; unless otherwise specified. Symbol Parameter td1 td2 td3 td4 td5 td6 td7 td8 td9 delay time; VSTAB to high voltage before TXON goes HIGH delay time; RF signal on RFI_HB or RFI_LB before PC ramp-up delay time; PC start of ramp-up after TXON goes HIGH delay time; TXON to LOW after transition of PC to off condition delay time; VSTAB to 0 V, after TXON goes LOW delay time; change of BAND after TXON goes LOW delay time; removal of RF signal on RFI_HB or RFI_LB after transition of PC to off condition time between PC ramp-up and actual PL increase Min 0 0 10 0 10 0 0 Typ Max Unit 3 µs µs µs µs µs µs µs µs µs delay time; BAND to LOW or HIGH before TXON goes HIGH 0 9397 750 14011 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 01 — 2 February 2005 5 of 22 www.DataSheet4U.com Philips Semiconductors BGY288 Power amplifier with integrated control loop 6.1 Ramp-up VSTAB voltage must be available at minimum td1 before TXON goes HIGH (power control loop activates). BAND selects the correct transmit channel (GSM850/EGSM900, or DCS1800/PCS1900). BAND must be at the correct value before the rising edge of TXON. The transition of TXON to HIGH enables the power control loop; the TXON minimum td4 period is a set-up time which allows the correct internal biasing conditions and the charge on the integration capacitors to be at the correct starting value before PC starts to increase. RF power must be present at the input of the selected channel (PD(LB) or PD(HB)) before PC starts to ramp-up. The required RF output power level is reached by increasing PC in steps to the corresponding voltage level. The sequence of PC steps can be chosen to have approximately a quarter cosine wave ramp-up of PL(LB) or PL(HB) in order to prevent violation of the GSM power mask, and at the same time prevent violation of the spectrum due to transients. To avoid violation of the lowest power level in the GSM power mask (indicated by *; see Figure 3), the BGY288 provides sufficient isolation when TXON goes HIGH with PC at minimum value and RF power at input of power amplifier. In LB TX mode, the system specification for maximum output power of the handset is −36 dBm. In HB TX mode, the system specification for maximum output power of the handset is −48 dBm. In BGY288 transmit mode, the handset antenna switch can be used to provide isolation between the power amplifier and the antenna by setting the antenna switch to Rx mode. This condition is used for the transmit mode isolation parameters given in