FINAL
Am27C128
128 Kilobit (16 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time — Speed options as fast as 45 ns s Low power consumption — 20 µA typical CMOS standby current s JEDEC-approved pinout s Single +5 V power supply s ±10% power supply tolerance standard s 100% Flashrite™ programming — Typical programming time of 2 seconds s Latch-up protected to 100 mA from –1 V to VCC + 1 V s High noise immunity s Versatile features for simple interfacing — Both CMOS and TTL input/output compatibility — Two line control functions s Standard 28-pin DIP, PDIP, and 32-pin PLCC packages
GENERAL DESCRIPTION
The Am27C128 is a 128-Kbit, ultraviolet erasable programmable read-only memory. It is organized as 16 Kwords by 8 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. Products are available in windowed ceramic DIP packages, as well as plastic one time programmable (OTP) PDIP and PLCC packages. Data can be typically accessed in less than 45 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 80 mW in active mode, and 100 µW in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD’s Flashrite programming algorithm (100 µs pulses), resulting in a typical programming time of 2 seconds.
BLOCK DIAGRAM
VCC VSS VPP OE# CE# PGM# Output Enable Chip Enable and Prog Logic Y Decoder A0–A13 Address Inputs Output Buffers Data Outputs DQ0–DQ7
Y Gating
X Decoder
131,072 Bit Cell Matrix
11420E-1
Publication# 11420 Rev: E Amendment/0 Issue Date: May 1998
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options VCC = 5.0 V ± 5% VCC = 5.0 V ± 10% -45 45 45 30 -55 55 55 35 -70 70 70 40 -90 90 90 40 -120 120 120 50 -150 150 150 50 -200 200 200 50 250 250 50 Am27C128 -255
Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns)
CONNECTION DIAGRAMS Top View
DIP PLCC
PGM# (P#) A13
A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
2 3 4 5 6 7 8 9 10 11 12 13 14
27 26 25 24 23 22 21 20 19 18 17 16 15
PGM# (P#) A13 A8 A9 A11 OE# (G#) A10 CE # (E#) DQ7 DQ6 DQ5 DQ4 DQ3
11420E-2
4 3 2 1 32 31 30 A6 A5 A4 A3 A2 A1 A0 NC DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VSS DU DQ3 DQ4 DQ1 DQ2 DQ5 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE# (G#) A10 CE# (E#) DQ7 DQ6
VCC
A7 A12
VPP
VPP
1
28
VCC
DU
11420E-3
Notes: 1. JEDEC nomenclature is in parenthesis. 2. Don’t use (DU) for PLCC.
PIN DESIGNATIONS
A0–A13 CE# (E#) DQ0–DQ7 OE# (G#) PGM# (P#) VCC VPP VSS NC = Address Inputs = Chip Enable Input = Data Input/Outputs = Output Enable Input = Program Enable Input
LOGIC SYMBOL
14 A0–A13 DQ0–DQ7 CE# (E#) 8
= VCC Supply Voltage = Program Voltage Input = Ground = No Internal Connection
PMG# (P#) OE# (G#)
11420E-4
2
Am27C128
ORDERING INFORMATION UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
AM27C128
-45
D
C
B
OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE D = 28-Pin Ceramic DIP (CDV028) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION Am27C128 128 Kilobit (16 K x 8-Bit) CMOS UV EPROM
Valid Combinations AM27C128-45 DC, DCB, DI, DIB AM27C128-55 AM27C128-70 AM27C128-90 AM27C128-120 AM27C128-150 AM27C128-200 AM27C128-255 VCC = 5.0 V ± 5% DC, DCB, DI, DIB DC, DCB, DI, DIB, DE, DEB
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am27C128
3
ORDERING INFORMATION OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
AM27C128
-55
P
C
OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) PACKAGE TYPE P = 28-Pin Plastic DIP (PD 028) J = 32-Pin Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION Am27C128 128 Kilobit (16 K x 8-Bit) CMOS OTP EPROM
Valid Combinations AM27C128-55 AM27C128-70 AM27C128-90 AM27C128-120 AM27C128-150 AM27C128-200 AM27C128-255 JC, PC, JI, PI
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
Am27C128
FUNCTIONAL DESCRIPTION Device Erasure
In order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be obtained by exposure to an ultraviolet lamp—wavelength of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20 minutes. The device should be directly under and about one inch from the source, and all filters should be removed from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000 Å, such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, exposure to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance.
VPP = 12.75 V ± 0.25 V and PGM# LOW will program that particular device. A high-level CE# input inhibits the other devices from being programmed.
Program Verify
A verification should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE# and CE#, at VIL, PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Autoselect Mode
The autoselect mode provides manufacturer and device identification through identifier codes on DQ0– DQ7. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device. To activate this mode, the programming equipment must force VH on address line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH (that is, changing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit.
Device Programming
Upon delivery, or after each erasure, the device has all of its bits in the “ONE”, or HIGH state. “ZEROs” are loaded into the device through the programming procedure. The device enters the programming mode when 12.75 V ± 0.25 V is applied to the VPP pin, and CE# and PGM# are at VIL. For programming, the data to be programmed is applied 8 bits in parallel to the data pins. The flowchar t in the Programming section of the EPROM Products Data Book (Section 5, Figure 5-1) shows AMD’s Flashrite algorithm. The Flashrite algorithm reduces programming time by using a 100 µs programming pulse and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while sequencing through each address of the device. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Please refer to Section 5 of the EPROM Products Data Book for additional programming information and specifications.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#) and Output Enable (OE#) must be driven low. CE# controls the power to the device and is typically used to select the device. OE# enables the device to output data, independent of device selection. Addresses must be stable for at least tACC –tOE. Refer to the Switching Waveforms section for the timing diagram.
Standby Mode
The device enters the CMOS standby mode when CE# is at VCC ± 0.3 V. Maximum VCC current is reduced to 100 µA. The device enters the TTL-standby mode when CE# is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a two-line control function provides: s Low memory power dissipation, and s Assurance that output bus contention will not occur. CE# should be decoded and used as the primary device-selecting function, while OE# be made a common
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for CE#, all like inputs of the devices may be common. A TTL low-level program pulse applied to one device’s CE# input with
Am27C128
5
connection to all devices in the array and connected to the R
