High Performance/ 80C186-/80C188-Compatible and 80L186-/80L188-Compatible/ 16-Bit Embedded Microcontrollers

Am186™ES and Am188™ES User’s Manual © 1997 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in its products without notice in order to improve design or performance characteristics. The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. 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Expert technical assistance is available from the worldwide staff of AMD field application engineers and factory support staff to answer E86™ family hardware and software development questions. Hotline and World Wide Web Support For answers to technical questions, AMD provides a toll-free number for direct access to our corporate applications hotline. Also available is the AMD World Wide Web home page and FTP site, which provides the latest E86 family product information, including technical information and data on upcoming product releases. For technical support questions on all E86 products, send E-mail to lpd.support@amd.com. Corporate Applications Hotline (800) 222-9323 44-(0) 1276-803-299 toll-free for U.S. U.K. and Europe hotline World Wide Web Home Page and FTP Site To access the AMD home page go to http://www.amd.com. To download documents and software, ftp to ftp.amd.com and log on as anonymous using your E-mail address as a password. Or via your web browser, go to ftp://ftp.amd.com. Questions, requests, and input concerning AMD’s WWW pages can be sent via E-mail to webmaster@amd.com. Documentation and Literature Free E86 family information such as data books, user’s manuals, data sheets, application notes, the FusionE86SM Partner Solutions Catalog, and other literature is available with a simple phone call. Internationally, contact your local AMD sales office for complete E86 family literature. Literature Ordering (800) 222-9323 (512) 602-5651 (512) 602-7639 (800) 222-9323 toll-free for U.S. and Canada direct dial worldwide fax AMD Facts-On-Demand™ faxback service toll-free for U.S. and Canada iii iv TABLE OF CONTENTS PREFACE INTRODUCTION AND OVERVIEW DESIGN PHILOSOPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PURPOSE OF THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTENDED AUDIENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USER’S MANUAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMD DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E86 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii xiii xiii xiii xiv xiv CHAPTER 1 FEATURES AND PERFORMANCE 1.1 KEY FEATURES AND BENEFITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 DISTINCTIVE CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 APPLICATION CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3.2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 PROGRAMMING 2.1 REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 Processor Status Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 MEMORY ORGANIZATION AND ADDRESS GENERATION . . . . . . . . . 2-3 2.3 I/O SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.5 SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.6 DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 SYSTEM OVERVIEW 3.1 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Pins That Are Used by Emulators . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.2 BUS OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.3 BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.3.1 Nonmultiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.3.2 Static Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.3.3 Byte Write Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.3.4 Pseudo Static RAM (PSRAM) Support . . . . . . . . . . . . . . . . . . . . 3-24 3.4 CLOCK AND POWER MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . 3-25 3.4.1 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.4.2 Crystal-Driven Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.4.3 External Source Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.4.4 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.4.5 Power-Save Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 PERIPHERAL CONTROL BLOCK 4.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 Peripheral Control Block Relocation Register (RELREG, Offset FEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.1.2 Reset Configuration Register (RESCON, Offset F6h). . . . . . . . . . 4-4 4.1.3 Processor Release Level Register (PRL, Offset F4h) . . . . . . . . . . 4-5 4.1.4 Auxiliary Configuration Register (AUXCON, Offset F2h). . . . . . . . 4-6 4.1.5 System Configuration Register (SYSCON, Offset F0h) . . . . . . . . 4-7 CHAPTER 2 CHAPTER 3 CHAPTER 4 Table of Contents v 4.2 CHAPTER 5 INITIALIZATION AND PROCESSOR RESET . . . . . . . . . . . . . . . . . . . . . 4-8 CHIP SELECT UNIT 5.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 CHIP SELECT TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 READY AND WAIT-STATE PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 5-2 5.4 CHIP SELECT OVERLAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.5 CHIP SELECT REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.5.1 Upper Memory Chip Select Register (UMCS, Offset A0h) . . . . . . 5-4 5.5.2 Low Memory Chip Select Register (LMCS, Offset A2h) . . . . . . . . 5-6 5.5.3 Midrange Memory Chip Select Register (MMCS, Offset A6h) . . . 5-8 5.5.4 PCS and MCS Auxiliary Register (MPCS, Offset A8h) . . . . . . . . 5-10 5.5.5 Peripheral Chip Select Register (PACS, Offset A4h) . . . . . . . . . 5-12 REFRESH CONTROL UNIT 6.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 Memory Partition Register (MDRAM, Offset E0h) . . . . . . . . . . . . 6-1 6.1.2 Clock Prescaler Register (CDRAM, Offset E2h) . . . . . . . . . . . . . . 6-2 6.1.3 Enable RCU Register (EDRAM, Offset E4h) . . . . . . . . . . . . . . . . 6-2 6.1.4 Watchdog Timer Control Register (WDTCON, Offset E6h). . . . . . 6-3 INTERRUPT CONTROL UNIT 7.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.1 Definitions of Interrupt Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.2 Interrupt Conditions and Sequence . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.1.3 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.1.4 Software Exceptions, Traps, and NMI . . . . . . . . . . . . . . . . . . . . . . 7-7 7.1.5 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.1.6 Interrupt Controller Reset Conditions . . . . . . . . . . . . . . . . . . . . . . 7-9 7.2 MASTER MODE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.1 Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.2 Cascade Mode . . . . . . . . . . . . . . . . . . . . . . . . .