Low IF WDCT 5.8 GHz Transceiver

Features • • • • • • • • • • 5.8 GHz Transceiver 5 dBm TX Output Power –97 dBm Sensitivity 1152 kBit/s Data-rate Supply-voltage Range 2.9V to 3.6V Low IF Receiver Low Current Consumption Few Low Cost External Components No Mechanical Adjustment Required Small 32 pin 5 mm × 5 mm QFN Package Applications • • • • 5.8 GHz Digital Cordless Phones Game Controllers Wireless Head Set FCC Part 15 Compliant Radio Link Low IF WDCT 5.8 GHz Transceiver ATR2820 Preliminary 1. Description The ATR2820 is a single chip RF-transceiver for applications in the 5.8 GHz ISM band. The QFN32 packaged IC is a complete transceiver including image rejection mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, integrated PLL with fully integrated VCO. No mechanical adjustment is necessary in production. www.DataSheet4U.com 4704D–DECT–11/06 Figure 1-1. Block Diagram REG_DEC VS VREG IREF VS_SYNA VS_SYND VS_IFA VS_IFD VS_TRX BP LIMITER DIGITAL DEMOD RX_DATA VREG_VCO VCO REG BIAS LNA RX_IN IR-MIXER RSSI RON_OUT RX_ON OUTPUT Buffer CLOCK DATA ENABLE RX_ON TX_ON HBS BUS PA TX_OUT VCO PLL CTRL LOGIC TX MOD CP/VT I COMP REF CLK www.DataSheet4U.com 2. Pin Configuration Figure 2-1. Pinning QFN32 – 5 mm × 5 mm ENABLE DATA CLOCK TEST_29 RX_DATA TX_ON RX_ON TEST_25 32 31 30 29 28 27 26 25 HBS REF_CLK RSSI VS_IFA VS_IFD TEST_6 TX_MOD IREF 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 RON_OUT NC TX_OUT NC RX_IN1 RX_IN2 NC VS_TRX ATR2820 Paddle on GND 9 10 11 12 13 14 15 16 NC VS_SYND VS_SYNA I_COMP VS_VREG CP/VT REG_DEC VREG_VCO 2 ATR2820 [Preliminary] 4704D–DECT–11/06 ATR2820 [Preliminary] Table 2-1. Pin Paddle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Description Symbol GND HBS REF_CLK RSSI VS_IFA VS_IFD TEST_6 TX_MOD IREF NC VS_SYND VS_SYNA I_COMP VS_VREG CP/VT REG_DEC VREG_VCO VS_TRX NC RX_IN2 RX_IN1 NC TX_OUT NC RON_OUT TEST_25 RX_ON TX_ON RX_DATA TEST_29 CLOCK DATA ENABLE Function Ground Handset/Basemode select: High = Basemode; Low = Handsetmode Reference frequency input Received signal strength indicator output Supply voltage for analog part of the IF circuit Supply voltage for digital part of the IF circuit Test pin Input for analog TX data signal External resistor for bias circuit Not connected Supply voltage for digital part of the PLL Supply voltage for analog part of the PLL External resistor for compensation current reference Supply voltage for VCO voltage regulator Charge-pump output / VCO tuning voltage input Decoupling pin for VCO voltage regulator VCO voltage regulator output Supply voltage for transmitter and receiver Not connected www.DataSheet4U.com Differential receiver input 2 Differential receiver input 1 Not connected TX driver amplifier output Not connected RXON output Test pin RX control input TX control input RX data output Test pin 3-wire-bus: Clock input 3-wire-bus: Data input 3-wire-bus: Enable input 3 4704D–DECT–11/06 Table 2-2. Pin Paddle Pin Description Input/Output Circuits Symbol GND Function Ground Configuration 1 26 27 29 30 31 HBS RX_ON TX_ON TEST_29 CLOCK DATA Digital Input (internal pull down resistor) 1, 26, 27, 29, 30, 31, 2 REF_CLK Reference frequency input 2 www.DataSheet4U.com 3 RSSI Receive signal strength indicator output 3 4 5 6 VS_IFA VS_IFD TEST_6 Supply voltage for analog part of the IF circuit Supply voltage for digital part of the IF circuit Test pin 7 TX_MOD Modulation input for analog TX data 7 4 ATR2820 [Preliminary] 4704D–DECT–11/06 ATR2820 [Preliminary] Table 2-2. Pin Pin Description Input/Output Circuits Symbol Function Configuration 8 IREF External resistor for bias circuit 8 9 10 11 NC VS_SYND VS_SYNA Not connected Supply voltage for digital part of the PLL Supply voltage for analog part of the PLL 12 I_COMP External resistor for compensation current reference 12 www.DataSheet4U.com 13 VS_VREG Supply voltage for VCO voltage regulator 14 CP/VT Charge-pump output / VCO tuning voltage input 14 5 4704D–DECT–11/06 Table 2-2. Pin Pin Description Input/Output Circuits Symbol Function Configuration 15 16 REG_DEC Decoupling pin for VCO_REG VREG_VCO VCO voltage regulator output 15 16 17 18 VS_TRX NC Supply voltage for transmitter receiver Not connected 19 20 RX_IN2 RX_IN1 Differential receiver input 2 Differential receiver input 1 19 20 www.DataSheet4U.com 21 NC Not connected 22 22 TX_OUT TX driver amplifier output 23 NC Not connected 24 RON_OUT RXON output 24 6 ATR2820 [Preliminary] 4704D–DECT–11/06 ATR2820 [Preliminary] Table 2-2. Pin Pin Description Input/Output Circuits Symbol Function Configuration 25 TEST_25 Test input 25 28 RX_DATA RX data output 28 www.DataSheet4U.com 32 ENABLE 3-wire-bus: Enable input (internal pullup resitor) 32 7 4704D–DECT–11/06 3. Functional Description 3.1 General The 5.8 GHz transceiver supports a data rate of 1152 kBit/s. 3.2 Transmitter The analog transmit data at TX_MOD (externally Gaussian filtered) is fed to the fully integrated VCO operating at the output frequency. The VCO signal is buffered by an internal preamplifier PA. This preamplifier supplies typically 5 dBm output power at TX_OUT. 3.3 Receiver The receiver consists of an LNA followed by the IR_MIXER. The IR_MIXER is driven by a 0/90 degree phase shifter from the VCO. The channel filtering of the IF signal (1.728 MHz) is done in the active polyphase filter. After a limiting amplifier the signal is converted from analog to digital by an ADC. Digital signal processing extracts the frequency information and delivers receive data. 3.4 PLL The PLL consists of a 8 bit main counter, a 5 bit swallow counter with a 32/33 modulus prescaler. The frequency/phase detector comparison frequency is 864 kHz. Open loop modulation is supported. The VCO is fully integrated, using on-chip inductors and varactors. The output signal is buffered to the TX_PA, 0/90 degree phase shifter for the IR_MIXER and to the modulus prescaler of the www.DataSheet4U.com PLL. 3.5 Serial Bus Programming The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. When the enable signal has returned to high condition, the programmed information is active. Additional leading bits are ignored and there is no check made about the number of clock pulses during enable low condition. The programming of the transceiver is done by a 16 bit data word in Normal Mode or by a 24 bit data word in Enhanced Mode. Normal Mode uses TX_ON respectively RX_ON pin to switch on the TX respectively RX blocks. The Enhanced Mode does this internally by programming the delay time bits D16 to D23. 3.6 Power Supply An integrated bandgap-stabilized voltage regulator supplies the VCO. Power up state is activated by the first rising edge of the CLOCK signal on the 3-wire bus interface. Power down state is activated either on the rising edge of the ENABLE signal on the 3-wire bus interface (Enhanced Mode) or by the falling edge of the TX_ON resp. RX_ON control signal (Normal Mode). If the transceiver supply voltage is switched off e.g., by means of an external regulator, all digital inputs must be kept on low level to insure the low standby current and not to provide supply current via the ESD protection devices. 8 ATR2820 [Preliminary] 4704D–DECT–11/06 ATR2820 [Preliminary] Figure 3-1. PLL Principle Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD × (SMC × 32 + SSC) external loop filter Phase frequency detector PD fPD = 864 kHz PA driver Charge pump VCO VCO Buffer Mixer Reference counter RC REF_CLK 10.368 MHz 13.824 MHz PLL reference Frequency REF_CLK Baseband Controller www.DataSheet4U.com Analog TX DATA The following table shows the possible LO frequencies for RX and TX in the 5.8 GHz ISM band. There are 142 channels available. Every second channel can be used without overlap in the spectrum. Table 3-1. Mode Channel Table fIF/kHz Channel C0 C1 fANT/MHz 5725.728 5726.592 ... 5846.688 5847.552 5725.728 5726.592 ... 5846.688 5847.552 fVCO/MHz 5725.728 5726.592 ... 5846.688 5847.552 5727.456 5728.320 ... 5848.416 5849.280 SMC 207 207 ... 211 211 207 207 ... 211 211 SSC 3 4 ... 15 16 5 6 ... 17 18 N 6627 6628 ... 6767 6768 6629 6630 ... 6769 6770 TX – ... C140 C141 C0 C1 RX 1728 ... C140 C141 Formula: TX: fANT = fVCO = 864 kHz × (32 × SMC + SSC) RX: fANT = 864 kHz × (32 × SMC + SSC – 2) 9 4704D–DECT–11/06 3.7 3.7.1 Bus Protocol Formats Normal Mode MSB Byte2 Data bits D15 0 D14 0 D13 DR D12 0 D11 0 D10 0 D9 TX D8 RC D7 D6 MC D5 D4 D3 D2 SC D1 D0 Byte1 LSB 3.7.2 MSB Enhanced Mode LSB Byte3 Byte2 Byte1 Data bits D23 D22 D21 D20 D19 D18 D17 D16 D15 1 D14 1 D13 DR D12 0 D11 0 D10 0 D9 TX D8 RC D7 D6 MC D5 D4 D3 D2 SC D1 D0 DELAY 3.7.3 PLL Settings RC, MC and SC bits are controlling the PLL frequency according to Table 3-2, Table 3-3 and Table 3-4. Table 3-2. Reference Counter Bit D8 www.DataSheet4U.com RC (Reference Counter) REF_CLK 10.368 MHz 13.824 MHz D8 0 1 Table 3-3. Main Counter Bits D5-D7 MC (Main Counter) D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 SMC 206 207 208 209 210 211 212 213 10 ATR2820 [Preliminary] 4704D–DECT–11/06 ATR2820 [Preliminary] Table 3-4. Swallow Counter Bits D0-D4 SC (Swallow Counter) D4 0 0 0 ... 1 1 1 D3 0 0 0 ... 1 1 1 D2 0 0 0 ... 1 1 1 D1 0 0 1 ... 0 1 1 D0 0 1 0 ... 1 0 1 SSC 0 1 2 ... 29 30 31 3.7.4 TX Mode ON/OFF The TX bit is used to prepare the ATR2820 for a TX or RX slot. The transmit or receive mode is later activated by the TX_ON respectively RX_ON signal. Table 3-5. D9 0 1 With Bit D9 TRX RX TX 3.7.5 Data Recovery www.DataSheet4U.com The DR bit switches the internal data recovery circuit on. Table 3-6. D13 0 1 With