Features
• High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture
– 131 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-chip 2-cycle Multiplier Non-volatile Program and Data Memories – 4/8/16K Bytes of In-System Self-Programmable Flash (ATmega48/88/168) Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 256/512/512 Bytes EEPROM (ATmega48/88/168) Endurance: 100,000 Write/Erase Cycles – 512/1K/1K Byte Internal SRAM (ATmega48/88/168) – Programming Lock for Software Security Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Six PWM Channels – 8-channel 10-bit ADC in TQFP and QFN/MLF package – 6-channel 10-bit ADC in PDIP Package – Programmable Serial USART – Master/Slave SPI Serial Interface – Byte-oriented 2-wire Serial Interface (Philips I2C compatible) www.DataSheet4U.com – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages – 23 Programmable I/O Lines – 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF Operating Voltage: – 1.8 - 5.5V for ATmega48V/88V/168V – 2.7 - 5.5V for ATmega48/88/168 Temperature Range: – -40°C to 85°C Speed Grade: – ATmega48V/88V/168V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V – ATmega48/88/168: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Low Power Consumption – Active Mode: 250 µA at 1 MHz, 1.8V 15 µA at 32 kHz, 1.8V (including Oscillator) – Power-down Mode: 0.1µA at 1.8V
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8-bit Microcontroller with 8K Bytes In-System Programmable Flash ATmega48/V ATmega88/V * ATmega168/V * * Preliminary
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Rev. 2545J–AVR–12/06
1. Pin Configurations
Figure 1-1. Pinout ATmega48/88/168
TQFP Top View
PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10)
PDIP
(PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 GND VCC GND VCC (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) ADC7 GND AREF ADC6 AVCC PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT4/MISO) PB4
(PCINT14/RESET) PC6 (PCINT16/RXD) PD0 (PCINT17/TXD) PD1 (PCINT18/INT0) PD2 (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 VCC GND (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 (PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) GND AREF AVCC PB5 (SCK/PCINT5) PB4 (MISO/PCINT4) PB3 (MOSI/OC2A/PCINT3) PB2 (SS/OC1B/PCINT2) PB1 (OC1A/PCINT1)
32 31 30 29 28 27 26 25
28 MLF Top View
PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11)
32 MLF Top View
PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) 32 31 30 29 28 27 26 25
28 27 26 25 24 23 22
(PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 VCC GND (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 (PCINT21/OC0B/T1) PD5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
21 20 19 18 17 16 15
PC2 (ADC2/PCINT10) PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) GND AREF AVCC PB5 (SCK/PCINT5)
(PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 GND VCC GND VCC (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) ADC7 GND AREF ADC6 AVCC PB5 (SCK/PCINT5)
(PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT4/MISO) PB4
NOTE: Bottom pad should be soldered to ground.
NOTE: Bottom pad should be soldered to ground.
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ATmega48/88/168
2545J–AVR–12/06
(PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT4/MISO) PB4
ATmega48/88/168
1.1
1.1.1
Pin Descriptions
VCC Digital supply voltage.
1.1.2
GND Ground.
1.1.3
Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page 78 and ”System Clock and Clock Options” on page 27.
1.1.4
Port C (PC5:0) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
1.1.5
PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 27-3 on page 307. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page 81.
1.1.6
Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
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2545J–AVR–12/06
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page 84. 1.1.7 AVCC AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC. 1.1.8 AREF AREF is the analog reference pin for the A/D Converter. 1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only) In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels.
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ATmega48/88/168
2545J–AVR–12/06
ATmega48/88/168
2. Overview
The ATmega48/88/168 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48/88/168 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
GND VCC
Watchdog Timer Watchdog Oscillator
Power Supervision POR / BOD & RESET
debugWIRE
PROGRAM LOGIC
Oscillator Circuits / Clock Generation
Flash
SRAM
CPU EEPROM
AVCC AREF GND
8bit T/C 0
16bit T/C 1
A/D Conv.
2
DATABUS
8bit T/C 2
Analog Comp.
Internal Bandgap
6
USART 0
SPI
TWI
PORT D (8)
PORT B (8)
PORT C (7)
RESET XTAL[1..2]
PD[0..7]
PB[0..7]
PC[0..6]
ADC[6..7]
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting
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architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega48/88/168 provides the following features: 4K/8K/16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM, 512/1K/1K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial I
