High Speed CPLD

www.DataSheet4U.com Features • High-performance Fully CMOS, Electrically-erasable Complex Programmable Logic Device – 64 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 5.0 ns Pin-to-pin Propagation Delay – Registered Operation up to 333 MHz – Enhanced Routing Resources – Optimized for 1.8V Operation – 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V – SSTL2-1 and SSTL3-1 Receiver In-System Programming (ISP) Supported – 1.8V ISP Using IEEE 1532 (JTAG) Interface – Boundary-scan Testing to IEEE JTAG Std. 1149.1 Supported Flexible Logic Macrocell – D/T/Latch Configurable Flip-flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate with Low Output Drive – Programmable Open Collector Output Option – Maximum Logic Utilization by Burying a Register with a Combinatorial Output and Vice Versa Fully Green (RoHS Compliant) 10 µA Standby Power Saving Option During Operation Using PD1, PD2 Pins Programmable Pin-keeper Option on Inputs and I/Os Programmable Schmitt Trigger Option on Input and I/O Pins Programmable Input and I/O Pull-up Option (per Pin) Unused Pins Can Be Configured as Ground (Optional) Available in Commercial and Industrial Temperature Ranges Available in 100-lead TQFP Advanced Digital CMOS Technology – 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20-year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity Security Fuse Feature Hot-Socketing Supported • Highperformance CPLD ATF1504BE • • • • • • • • • • • • • 3637A–PLD–11/06 www.DataSheet4U.com Enhanced Features • • • • • • • • • Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) Output Enable Product Terms Outputs Can Be Configured for High or Low Drive Combinatorial Output with Registered Feedback and Vice Versa within each Macrocell Three Global Clock Pins Fast Registered Input from Product Term Pull-up Option on TMS and TDI JTAG Pins OTF (On-the-Fly) Reconfiguration Mode DRA (Direct Reconfiguration Access) 1. Description The ATF1504BE is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1504BE’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1504BE has up to 64 bi-directional I/O pins and four dedicated input pins. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Figures 1-1 and 1-2 shows the pin assignments for the 100-lead and 44-lead TQFP packages respectively. 2 ATF1504BE 3637A–PLD–11/06 www.DataSheet4U.com ATF1504BE Figure 1-1. 100-lead TQFP Top View I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIOB I/O I/O I/O NC NC I/O NC NC VCCIOA I/O/TDI NC I/O NC I/O I/O I/O GND VREFA/I/O/PD1 I/O I/O I/O/TMS I/O I/O VCCIOA I/O I/O I/O NC I/O NC I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O GND I/O/TDO NC I/O NC I/O I/O I/O VCCIOB I/O I/O I/O I/O/TCK I/O I/O/VREFB GND I/O I/O I/O NC I/O NC I/O VCCIOB GND NC NC I/O I/O I/O I/O I/O VCCIOA I/O I/O I/O GND VCCINT I/O I/O I/O/PD2 GND I/O I/O I/O I/O I/O NC NC 3 3637A–PLD–11/06 www.DataSheet4U.com Figure 1-2. 44-lead TQFP Top View I/O I/O I/O VCCINT GCLK2/OE2/I GCLR/I I/OE1 GCLK1/I GND GCLK3/I/O I/O 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 I/O/TDI I/O I/O GND PD1/I/O I/O TMS/I/O I/O VCCIOA I/O I/O 1 2 3 4 5 6 7 8 9 10 11 I/O I/O/TDO I/O I/O VCCIOB I/O I/O I/O/TCK I/O GND I/O 4 ATF1504BE 3637A–PLD–11/06 I/O I/O I/O I/O GND VCCINT I/O PD2/I/O I/O I/O I/O www.DataSheet4U.com ATF1504BE Figure 1-3. Block Diagram 8 or 16 8 or 16 I/O (MC64)/GCLK3 Each of the 64 macrocells generates a buried feedback signal that goes to the global bus (see Figure 1-3). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1504BE allows fast, efficient generation of complex logic functions. The ATF1504BE contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1504BE macrocell, shown in Figure 1-4, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs. A security fuse, when programmed, protects the contents of the ATF1504BE. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. The ATF1504BE device is an In-System Programming (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1532), and is fully compliant with JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. 5 3637A–PLD–11/06 www.DataSheet4U.com Figure 1-4. ATF1504BE Macrocell BURIED FEEDBACK SCHMITT TRIGGER 1.1 Product Terms and Select Mux Each ATF1504BE macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration. 1.2 OR/XOR/CASCADE Logic The ATF1504BE’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with minimal additional delay. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. 6 ATF1504BE 3637A–PLD–11/06 www.DataSheet4U.com ATF1504BE 1.3 Flip-flop The ATF1504BE’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. The clock itself can be any one of the Global CLK signals (GCK[0 : 2]) or an individual product term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off. 1.4 Extra Feedback The ATF1504BE macrocell output can be selected as registered or combinatorial. The extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (This enhancement function is automatically implemented by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second latch within a macrocell. 1.5 I/O Control The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or bi-directional pin. The output enable for each macrocell can be selected from the true or complement of the two output enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software when the I/O is configured as an input or bi-directional pin. 1.6 Global Bus/Switch Matrix The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 64 macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the logic block. 1.7 Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional