(ATF15xxAE) 2nd Generation EE Complex Programmable Logic Devices

www.DataSheet4U.com Features • 2nd Generation EE Complex Programmable Logic Devices – 3.0V to 3.6V Operating Range with 5V Tolerant I/Os – 32 - 512 Macrocells with Enhanced Features – Pin-compatible with Industry-standard Devices – Speeds to 4.5 ns Maximum Pin-to-pin Delay – Registered Operation to 225 MHz Enhanced Macrocells with Logic Doubling™ Features – Bury Either Register or COM while Using the Other for Output – Dual Independent Feedback Allows Multiple Latch Functions per Macrocell – 5 Product Terms per Macrocell, Expandable to 40 per Macrocell with Cascade Logic, Plus 15 More with Foldback Logic – D/T/Latch Configurable Flip-flops plus Transparent Latches – Global and/or per Macrocell Register Control Signals – Global and/or per Macrocell Output Enable – Programmable Output Slew Rate per Macrocell – Programmable Output Open Collector Option per Macrocell – Fast Registered Input from Product Term Enhanced Connectivity – Single Level Switch Matrix for Maximum Routing Options – Up to 40 Inputs per Logic Block Advanced Power Management Features – ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and I/O for µA Level Standby Current on “L” versions – Pin-controlled 1 mA Standby Mode – Reduced-power Option per Macrocell – Automatic Power Down of Unused Macrocells – Programmable Pin-keeper Inputs and I/Os Available in Commercial and Industrial Temperature Ranges Available in All Popular Packages Including PLCC, PQFP, TQFP and BGA EE Technology – 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993 – Pull-up Option on JTAG Pins TMS and TDI IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG PCI-compliant Security Fuse Feature • ATF15xxAE Family Datasheet ATF1502AE(L) ATF1504AE(L) ATF1508AE(L) ATF1516AE(L) ATF1532AE(L) Preliminary • • • • • • • • • Rev. 2398E–12/01 1 General Description Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells in 1996, Atmel’s CPLD products have delivered extra IO connectivity and logic reusability. Atmel’s commitment to efficient, flexible architecture has continued with the current Atmel ATF15xx Family of industry-standard, pin-compatible CPLDs. Atmel’s Logic Doubling architecture consists of wider fan-in, additional routing and clock options, combined with sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel enhanced macrocell includes double independent buried feedback that allows designers to pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for later revisions. The Atmel ATF15xx family delivers enhanced functionality and flexibility with no additional design effort and is highly cost effective. The Atmel ATF15xx Family includes all popular configurations and speeds. Table 1. ATF15xxAE Family Device Features Feature Usable Gates Macrocells Logic Blocks Max. # Pins Max. User I/Os TPD Grades (ns) ATF1502AE(L) ATF1504AE(L) ATF1508AE(L) ATF1516AE(L) ATF1532AE(L) 750 32 2 44 36 4, 7, 10(15) 1500 64 4 100 68 4, 7, 10(15) 3000 128 8 256 100 5, 7, 10(15) 6000 256 16 256 164 5, 7, 10(15) 12000 512 32 256 212 5, 7, 12(15) The Atmel ATF15xxAE Family includes pin-compatible products in all popular packages. Table 2. ATF15xxAE Family Device Packages and Number of Signal Pins(1)(2) Packages 44-pin PLCC 44-pin TQFP 49-ball BGA 84-pin PLCC 100-pin TQFP 100-ball BGA 144-pin TQFP 169-ball BGA 208-pin PQFP 256-ball BGA 100 68 68 ATF1502AE(L) 36 36 ATF1504AE(L) 36 36 41 68 84 84 100 100 164 164 176 212 84 84 120 120 ATF1508AE(L) ATF1516AE(L) ATF1532AE(L) Notes: 1. Contact Atmel for up-to-date information on device and package availability. 2. When the JTAG port is used for In System Programming (ISP) or Boundary-scan Testing (BST), the four associated pins become JTAG pins and are unavailable for user I/O. 2 ATF15xxAE Family 2398E–12/01 ATF15xxAE Family Functional Description The ATF15xxAE Family of 3.3 Volt supply, high-performance, high-density complex programmable logic devices (CPLDs) utilizes Atmel’s proven electrically-erasable technology. With up to 512 macrocells, they easily integrate logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF15xxAE Family’s enhanced macrocell architecture, switch matrices and routing increase usable gate count for new designs and increase odds of successful pin-locked design modifications while maintaining pin-compatibility with industry-standard CPLDs. The ATF15xxAE Family devices have four dedicated input pins and depending on the type of device and package, up to 208 bi-directional I/O pins. Each dedicated input pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each input and I/O pin also feeds into the global bus. The macrocells are organized into groups of sixteen called logic blocks. The switch matrix in each logic block selects 40 individual signals from the global bus. Macrocells within a given logic block may share their sixteen foldback signals on a regional foldback bus. Cascade logic between macrocells in the Logic Block allows fast, efficient generation of complex logic functions. All macrocells are capable of being I/Os; however, the actual number of I/O pins depends on the device and package type. The ATF15xxAE Family members contain two, four, eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a fan-in of 40 inputs from the switch matrix having access to up to 80 product terms. Unused macrocells are automatically disabled by the fitter software to decrease power consumption. A security fuse, when programmed, protects the contents of the other fuses. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. The ATF15xxAE Family devices are In-System Programmable (ISP) devices. They use the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and are fully-compliant with JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. Global Bus/Switch Matrix The global bus (Figure 1) contains all input and I/O pin signals as well as the buried feedback signals from all macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Up to 40 of these signals can be selected as inputs to the individual logic blocks by the fitter software. Atmel’s ATF15xx Family of CPLDs use a single level switch matrix signal distribution structure, where each logic block input has access to the same number of global bus inputs, maximizing the number of possible ways to route a global bus signal. This single level structure is in contrast with split switch matrix structures used by others in which routing a particular global bus input to a particular logic block input makes that signal unavailable to some other logic blocks, thus greatly limiting the available opportunities to route. The ATF15xxAE Family macrocell, shown in Figure 2, consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, foldback bus, a flip-flop and output buffer. Extra fan-in and signal routing are provided throughout. Each macrocell can generate a foldback logic term from the product term mux and a buried feedback with extra routing that go to the global bus. 3 2398E–12/01 Figure 1. ATF15xxAE Family Typical Block Diagram 2 to 16 N 2 to 16 N-1 4 ATF15xxAE Family 2398E–12/01 ATF15xxAE Family Figure 2. ATF15xxAE Family Macrocell with Enhanced Features In Red SWITCH REGIONAL MATRIX FOLDBACK OUTPUTS BUS CASIN 80 16 LOGIC FOLDBACK SWITCH MATRIX 40 PT1 PT2 1 PT3 GOE[0:5] 6 Product Term MUX 2 Q !Q AP I/O Pin D/T*/L Q I/O Pin 3 4 CK/CK/LE GCK[0:2] 3 CE SLEW RATE !Q OPEN COLLECTOR GOE SWITCH MATRIX GOE [0:5] 5 PT4 PT5 AR GCLEAR GLOBAL BUS Reduced Power Option CASOUT * T flip-flop synthesised Product Terms and Select Mux Within each macrocell are five product terms. Each product term may receive as its inputs any combination of the signals from the switch matrix or regional foldback bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the fitter software, which selects the optimum macrocell configuration. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate may be fed from the flip-flop output to emulate T- and JKtype flip-flops, or fed to the buried feedback to synthesize an extra latch. OR/XOR/ CASCADE Logic Foldback Bus Each macrocell can also generate a foldback product term. This signal goes to the regional bus and is available to the 16 macrocells in a given logic block.