Microcontroller

Features • 8-bit Microcontroller Compatible with MCS®51 Products • Enhanced 8051 Architecture – Single-clock Cycle per Byte Fetch – Up to 20 MIPS Throughput at 20 MHz Clock Frequency – Fully Static Operation: 0 Hz to 20 MHz – On-chip 2-cycle Hardware Multiplier – 128 x 8 Internal RAM – 4-level Interrupt Priority Nonvolatile Program Memory – 2K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: Minimum 10,000 Write/Erase Cycles – Data Retention: Minimum 10 Years – Serial Interface for Program Downloading – 32-byte Fast Page Programming Mode – 64-byte User Signature Array – 2-level Program Memory Lock for Software Security Peripheral Features – Two 16-bit Enhanced Timer/Counters – Two 8-bit PWM Outputs – Enhanced UART with Automatic Address Recognition and Framing Error Detection – Enhanced Master/Slave SPI with Double-buffered Send/Receive – Programmable Watchdog Timer with Software Reset – Analog Comparator with Selectable Interrupt and Debouncing – 8 General-purpose Interrupt Pins Special Microcontroller Features – Two-wire On-chip Debug Interface www.DataSheet4U.com – Brown-out Detection and Power-on Reset with Power-off Flag – Internal RC Oscillator – Low Power Idle and Power-down Modes – Interrupt Recovery from Power-down Mode I/O and Packages – Up to 14 Programmable I/O Lines – Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and Open-drain Modes – 5V Tolerant I/O – 16-lead TSSOP/SOIC/PDIP Operating Conditions – 2.4V to 5.5V VCC Voltage Range – -40° C to 85°C Temperature Range • • 8-bit Microcontroller with 2K Bytes Flash AT89LP216 Preliminary • • • 1. Description The AT89LP216 is a low-power, high-performance CMOS 8-bit microcontroller with 2K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The AT89LP216 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP216 CPU, instructions need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they 3621A–MICRO–6/06 have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reduces power consumption. The AT89LP216 provides the following standard features: 2K bytes of In-System Programmable Flash memory, 128 bytes of RAM, up to 12 I/O lines, two 16-bit timer/counters, two PWM outputs, a programmable watchdog timer, a full-duplex serial port, a serial peripheral interface, an internal RC oscillator, on-chip crystal oscillator, and a four-level, six-vector interrupt system. The two timer/counters in the AT89LP216 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition, the timer/counters may independently drive a pulse width modulation output. The I/O ports of the AT89LP216 can be independently configured in one of four operating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode provides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an interrupt using the general-purpose interrupt interface. The I/O pins of the AT89LP216 tolerate voltages higher than the device’s own power supply, up to 5.5V. When the device is supplied at 2.4V and all I/O ports receive 5.5V, the total back flowing current an all I/Os is less than 100 µA. 2. Pin Configuration 2.1 AT89LP216: 16-lead PDIP/SOIC/TSSOP (GPI5/MOSI) P1.5 (GPI7/SCK) P1.7 (GPI3/RST) P1.3 GND (GPI2) P1.2 (RXD) P3.0 (T0) P3.4 (XTAL1/INT0) P3.2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 P1.6 (MISO/GPI6) P1.4 (SS/GPI4) P1.1 (AIN1/GPI1) P1.0 (AIN0/GPI0) VCC P3.1 (TXD) P3.5 (T1) P3.3 (INT1/XTAL2/CLKOUT) 2 AT89LP216 [Preliminary] 3621A–MICRO–6/06 AT89LP216 [Preliminary] 3. Pin Description Table 3-1. Pin AT89LP216 Pin Description Symbol Type I/O I/O I I/O I/O I I/O I I I I I/O I I/O I I/O I/O I/O I Description P1.5: User-configurable I/O Port 1 bit 5. MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as slave, this pin is an input. GPI5: General-purpose Interrupt input 5. P1.7: User-configurable I/O Port 1 bit 7. SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is an input. GPI7: General-purpose Interrupt input 7. P1.3: User-configurable I/O Port 1 bit 3 (if Reset Fuse is disabled). RST: External Active-Low Reset input (if Reset Fuse is enabled. See “External Reset” on page 14.). GPI3: General-purpose Interrupt input 3. DCL: Serial Clock input for On-Chip Debug Interface when OCD is enabled. Ground P1.2: User-configurable I/O Port 1 bit 2. GPI2: General-purpose Interrupt input 2. P3.0: User-configurable I/O Port 3 bit 0. RXD: Serial Port Receiver Input. P3.4: User-configurable I/O Port 3 bit 4. T0: Timer/Counter 0 External Input or PWM Output. P3.2: User-configurable I/O Port 3 bit 2. XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits. It may be used as a port pin if the internal RC oscillator is selected as the clock source. DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and the internal RC oscillator is selected as the clock source. P3.3: User-configurable I/O Port 3 bit 3. XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the internal RC oscillator is selected as the clock source. CLKOUT: When the internal RC oscillator is selected as the clock source, may be used to output the internal clock divided by 2. DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and the external clock is selected as the clock source. P3.5: User-configurable I/O Port 3 bit 5. T1: Timer/Counter 1 External input or PWM output. P3.1: User-configurable I/O Port 3 bit 1. TXD: Serial Port Transmitter Output. Supply Voltage P1.0: User-configurable I/O Port 1 bit 0. AIN0: Analog Comparator Positive input. GPI0: General-purpose Interrupt input 0. P1.1: User-configurable I/O Port 1 bit 1. AIN1: Analog Comparator Negative input. GPI1: General-purpose Interrupt input 1 P1.4: User-configurable I/O Port 1 bit 4. SS: SPI slave select input. GPI4: General-purpose Interrupt input 4. P1.6: User-configurable I/O Port 1 bit 6. MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured as slave, this pin is an output. GPI6: General-purpose Interrupt input 6. 1 P1.5 2 P1.7 3 P1.3 4 5 6 7 GND P1.2 P3.0 P3.4 8 P3.2 I/O I/O O 9 P3.3 O I/O I/O I/O I/O O I I/O I I I/O I I I/O I I I/O I/O I 10 P3.5 11 12 13 P3.1 VDD P1.0 14 P1.1 15 P1.4 16 P1.6 3 3621A–MICRO–6/06 4. Block Diagram Figure 4-1. AT89LP216 Block Diagram Single Cycle 8051 CPU UART 2K Bytes Flash SPI 128 Bytes RAM Timer 0 Timer 1 Port 3 Configurable I/O Analog Comparator Port 1 Configurable I/O Watchdog Timer General-purpose Interrupt On-Chip RC Oscillator CPU Clock Configurable Oscillator Crystal or Resonator 5. Comparison to Standard 8051 The AT89LP216 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051. The differences from the standard 8051 are outlined in the following paragraphs. 5.1 System Clock The CPU clock frequency equals the external XTAL1 frequency. The oscillator is no longer divided by 2 to provide the internal clock, and x2 mode is not supported. 5.2 Instruction Execution with Single-cycle Fetch The CPU fetches one code byte from memory every clock cycle instead of every six clock cycles. This greatly increases the throughput of the CPU. As a consequence, the CPU no longer executes instructions in 12 to 48 clock cycles. Each instruction executes in only 1 to 4 clock cycles. See “Instruction Set Summary” on page 59. for more details. 4 AT89LP216 [Preliminary] 3621A–MICRO–6/06 AT89LP216 [Preliminary] 5.3 Interrupt Handling The interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In order for an interrupt to be serviced at the end of an instruction, its flag needs to have been latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of the previous instruction if the current instruction executes in only a single clock cycle. The external interrupt pins, INT0 and INT1, are sampled at every clock cycle instead of once every 12 clock cycles. Coupled with the shorter instruction timing and faster interrupt response, this leads to a higher maximum rate of incidence for the external interrupts. 5.4 Timer/Counters By default the Timer/Counters is incremented at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the increment rate. The TPS bits in the CLKREG SFR control the