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Features
• • • •
Compatible with MCS®51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.7V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable (ISP) Flash Memory – Serial Interface for Program Downloading – 32-byte Fast Page Programming Mode – 32-byte User Signature Array 2.4V to 5.5V VCC Operating Range Fully Static Operation: 0 Hz to 20 MHz 2-level Program Memory Lock 256 x 8 Internal RAM Hardware Multiplier 15 Programmable I/O Lines Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and Open-drain Modes Enhanced UART with Automatic Address Recognition and Framing Error Detection Enhanced SPI with Double-buffered Send/Receive Programmable Watchdog Timer with Software Reset 4-level Interrupt Priority Analog Comparator with Selectable Interrupt and Debouncing Two 16-bit Enhanced Timer/Counters with 8-bit PWM Brown-out Detector and Power-off Flag Internal Power-on Reset Low Power Idle and Power-down Modes DataSheet4U.com Interrupt Recovery from Power-down Mode
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8-bit Microcontroller with 2/4-Kbyte Flash AT89LP2052 AT89LP4052 Preliminary
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1. Description
The AT89LP2052/LP4052 is a low-power, high-performance CMOS 8-bit microcontroller with 2/4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The AT89LP2052/LP4052 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch required 6 clock cycles, forcing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP2052/LP4052 CPU, instructions need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reduces power consumption.
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The two timer/counters in the AT89LP2052/LP4052 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition both timer/counters may be configured as 8-bit Pulse Width Modulators with 8-bit prescalers. The I/O ports of the AT89LP2052/LP4052 can be independently configured in one of four operating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the ports are tri-stated. Push-pull output mode provides full CMOS drivers and open-drain mode provides just a pull-down.
2. Pin Configuration
2.1 20-lead PDIP/SOIC/TSSOP
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(VPP) RST 1 (RXD) P3.0 2 (TXD) P3.1 3 XTAL2 4 XTAL1 5 (INT0) P3.2 6 (INT1) P3.3 7 (T0) P3.4 8 DataSheet4U.com (T1) P3.5 9 GND 10
20 19 18 17 16 15 14 13 12 11
VCC P1.7 (SCK) P1.6 (MISO) P1.5 (MOSI) P1.4 (SS) P1.3 P1.2 P1.1 (AIN1) P1.0 (AIN0) P3.7 (SYSCLK)
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AT89LP2052/LP4052 [Preliminary]
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AT89LP2052/LP4052 [Preliminary]
3. Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol RST P3.0 P3.1 XTAL2 XTAL1 P3.2 P3.3 P3.4 P3.5 GND P3.7 P1.0 P1.1 P1.2 P1.3 P1.4 Type I I I/O I I/O O O I I/O I I/O I I/O I/O I/O I/O I I/O O I/O I I/O I I/O I/O I/O I I/O I/O I/O I/O I/O I/O I Description RST: External Active-High Reset input. VPP: Parallel Programming Voltage. Raise to 12V to enable programming. P3.0: User-configurable I/O Port 3 bit 0. RXD: Serial Port Receiver input. P3.1: User-configurable I/O Port 3 bit 1. TXD: Serial Port Transmitter output. XTAL2: Output from inverting oscillator amplifier. XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits. P3.2: User-configurable I/O Port 3 bit 2. INT0: External Interrupt 0 input. P3.3: User-configurable I/O Port 3 bit 3. INT1: External Interrupt 1input. P3.4: User-configurable I/O Port 3 bit 4. T0: Timer 0 Counter input or PWM output P3.5: User-configurable I/O Port 3 bit 5. T1: Timer 1 Counter input or PWM output Ground
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DataSheet4U.com P3.7: User-configurable I/O Port 3 bit 7. SYSCLK: System Clock Output when System Clock Fuse is enabled.
P1.0: User-configurable I/O Port 1 bit 0. AIN0: Analog Comparator Positive input. P1.1: User-configurable I/O Port 1 bit 1. AIN1: Analog Comparator Negative input. P1.2: User-configurable I/O Port 1 bit 2. P1.3: User-configurable I/O Port 1 bit 3 P1.4: User-configurable I/O Port 1 bit 4. SS: SPI slave select. P1.5: User-configurable I/O Port 1 bit 5. MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as slave, this pin is an input. P1.6: User-configurable I/O Port 1 bit 6. MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured as slave, this pin is an output. P1.7: User-configurable I/O Port 1 bit 7. SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is an input. Supply Voltage
17
P1.5
18
P1.6
19
P1.7
20
VCC
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4. Block Diagram
Single Cycle 8051 CPU 2/4-Kbyte Flash 256-Byte RAM
Port 3 Configurable I/O
UART
SPI
Timer 0 Timer 1 Analog Comparator Watchdog Timer Configurable Oscillator
Crystal or Resonator
Port 1 Configurable I/O
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CPU Clock DataSheet4U.com
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5. Memory Organization
The AT89LP2052/LP4052 uses a Harvard Architecture with separate address spaces for program and data memory. The program memory has a regular linear address space with support for up to 64K bytes of directly addressable application code. The data memory has 256 bytes of internal RAM which is divided into regions that may be accessed by different instruction classes. The AT89LP2052/LP4052 does not support external RAM.
5.1
Program Memory
The AT89LP2052/LP4052 contains 2/4K bytes of on-chip In-System Programmable Flash memory for program storage. The Flash memory has an endurance of at least 10,000 write/erase cycles. Section 22. “Programming the Flash Memory” on page 54 contains a detailed description on Flash Programming in ISP or Parallel Programming mode. The reset and interrupt vectors are located within the first 59 bytes of program memory (see Section 13. “Interrupts” on page 13). Constant tables can be allocated within the entire 2/4-Kbyte program memory address space for access by the MOVC instruction.
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AT89LP2052/LP4052 [Preliminary]
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AT89LP2052/LP4052 [Preliminary]
Figure 5-1. Program Memory Map
0FFF
07FF Program Memory AT89LP2052 0000 0000
Program Memory AT89LP4052
5.2
Data Memory
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The AT89LP2052/LP4052 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O memory. The lower 128 bytes of data memory may be accessed through both direct and indirect addressing. The upper 128 bytes of data memory and the 128 bytes of I/O memory share the same address space (see Figure 5-2). The upper 128 bytes of data memory may only be accessed using indirect addressing. The I/O memory can only be accessed through direct addressing and contains the Special Function Registers (SFRs). The lowest 32 bytes of data memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits (PSW.3 and PSW.4) select which register bank is in use. Instructions using register addressing will only access the currently specified bank. The AT89LP2052/LP4052 does not support external data DataShee memory. DataSheet4U.com Figure 5-2. Data Memory Map
FFH Accessible By Indirect Addressing Only Accessible By Direct Addressing
FFH
Upper 128 80H 7FH Lower 128
80H Accessible By Direct and Indirect Addressing Special Function Registers Ports Status and Control Bits Timers Registers Stack Pointer Accumulator (Etc.)
0
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6. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 6-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 6-1.
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H PSW* 0000 0000 SPCR 0000 0000 ACC* 0000 0000 B* 0000 0000
AT89LP2052/LP4052 SFR Map and Reset Values
0FFH 0F7H 0EFH 0E7H 0DFH 0D7H 0CFH P1M0 1111 1111 P1M1 0000 0000
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0C0H 0B8H 0B0H 0A8H 0A0H 98H 90H 88H 80H SCON* 0000 0000 P1* 1111 1111 TCON* 0000 0000 SBUF xxxx xxxx TCONB 0010 0100 TMOD 0000 0000 SP 0000 0111 RL0 0000 0000 TL0 0000 0000 DPL 0000 0000 RL1 0000 0000 TL1 0000 0000 DPH 0000 0000 RH0 0000 0000 TH0 0000 0000 RH1 0000 0000 TH1 0000 0000 SPDR xxxx xxxx PCON 000x 0000 ACSR xx00 0000 IP* x0x0 0000 P3* 1111 1111 IE* 00x0 0000 SADDR 0000 0000 SPSR 000x xx00 WDTRST (write-only) WDTCON 0000 x000 SADEN 0000 0000 IPH x0x0 0000
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P3M0 1111 1111
P3M1 0000 0000
0C7H 0BFH 0B7H 0AFH 0A7H 9FH 97H 8FH 87H
Note:
*These SFRs are bit-addressable.
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