Features
• Protocol
– UART Used as a Physical Layer – Based on the Intel Hex-type Records – Autobaud • In-System Programming – Read/Write Flash Memory – Read Device IDs – Block Erase – Full-chip Erase – Read/Write Configuration Bytes – Security Setting From ISP Command – Remote Application Start Command • In-Application Programming/Self-Programming – Read/Write Flash Memory – Read Device IDs – Block Erase – Read/Write Configuration Bytes – Bootloader Start
MP3 Microcontrollers
Description
This document describes the UART bootloader functionalities as well as the serial protocol to efficiently perform operations on the on-chip Flash memory. Additional information for the AT89C51SND1 product can be found in the AT89C51SND1 data sheet and the AT89C51SND1 errata sheet available on the Atmel web site, www.atmel.com. The bootloader software package (source code and binary) currently used for production is available from the Atmel web site.
AT89C51SND1 UART Bootloader
Bootloader Revision Revision 1.0.0 Revision 1.1.0
Purpose of Modifications New release increasing programming speed Bug fix in boot process
Date June 2002 October 2002
4241B–MP3–07/04
1
Functional Description
In-System Programming Capability
The AT89C51SND1 bootloader facilitates In-System Programming and In-Application Programming. In-System Programming (ISP) allows the user to program or reprogram a microcontroller’s on-chip Flash memory without removing it from the system and without the need of a pre-programmed application. The UART bootloader can manage a communication with a host through the serial network. It can also access and perform requested operations on the on-chip Flash memory.
In-Application Programming or SelfProgramming Capability
In-Application Programming (IAP) allows the reprogramming of a microcontroller’s onchip Flash memory without removing it from the system and while the embedded application is running. The UART bootloader contains some Application Programming Interface routines named API routines allowing IAP by using the user’s firmware.
Block Diagram
This section describes the different parts of the bootloader. Figure 1 shows the on-chip bootloader and IAP processes. Figure 1. Bootloader Process Description
External Host via the UART Protocol Communication On-chip User Application
ISP Communication Management
IAP User Call Management
Flash memory Management
Flash Memory
2
AT89C51SND1 UART Bootloader
4241B–MP3–07/04
AT89C51SND1 UART Bootloader
ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and an external device (host). The on-chip bootloader implements a serial protocol (see Section “Protocol”, page 9). This process translates serial communication frames (UART) into Flash memory accesses (read, write, erase, etc.). Several Application Program Interface (API) calls are available to the application program to selectively erase and program Flash pages. All calls are made through a common interface (API calls) included in the bootloader. The purpose of this process is to translate the application request into internal Flash memory operations. This process manages low level accesses to the Flash memory (performs read and write accesses).
User Call Management
Flash Memory Management
Bootloader Configuration
Configuration and Manufacturer Information The table below lists configuration and manufacturer byte information used by the bootloader. This information can be accessed through a set of API or ISP commands. Table 1. Configuration and Munfacturer Byte Information
Mnemonic BSB SBV SSB Manufacturer ID1: Family code ID2: Product Name ID3: Product Revision Description Boot Status Byte Software Boot Vector Software Security Byte Default Value FFh F0h FCh 58h D7h ECh FFh
Mapping and Default Value of Hardware Security Byte
The 4 Most Significant Bytes (MSB) of the Hardware Byte can be read/written by software (this area is called Fuse bits). The 4 Least Significant Bytes (LSB) can only be read by software and written by hardware in parallel mode (with parallel programmer devices). Table 2. Mapping and Default Value of HSB
Bit Position 7 6 5 4 3 2 1 0 Mnemonic X2B BLJB Reserved Reserved Reserved LB2 LB1 LB0 Default Value U P U U U P U U To lock the chip (see datasheet) Description To start in x1 mode To map the boot area in code area between F000hFFFFh
Note:
U: Unprogrammed = 1, P: Program = 0
3
4241B–MP3–07/04
Software Security Byte
The bootloader has Software Security Byte (SSB) to protect itself from user access or ISP access. The Software Security Byte (SSB) protects from ISP accesses. The command “Program Software Security Bit” can only write a higher priority level. There are three levels of security: • • level 0: NO_SECURITY (FFh) From level 0, one can write level 1 or level 2. level 1: WRITE_SECURITY (FEh) In this level it is impossible to write in the Flash memory, BSB and SBV. The bootloader returns an error message. From level 1, one can write only level 2. level 2: RD_WR_SECURITY (FCh) This is the default level. Level 2 forbids all read and write accesses to/from the Flash memory. The bootloader returns an error message.
•
Only a full-chip erase command can reset the software security bits. Table 3. Software Security Byte Levels
Level 0 Flash Fuse bit BSB & SBV SSB Manufacturer info Bootloader info Erase block Full chip erase Blank Check Any access allowed Any access allowed Any access allowed Any access allowed Read only access allowed Read only access allowed Allowed Allowed Allowed Level 1 Read only access allowed Read only access allowed Read only access allowed Write level2 allowed Read only access allowed Read only access allowed Not allowed Allowed Allowed Level 2 All access not allowed All access not allowed All access not allowed Read only access allowed Read only access allowed Read only access allowed Not allowed Allowed Allowed
Software Boot Vector
The Software Boot Vector (SBV) forces the execution of a user bootloader starting at address [SBV]00h in the application area (FM0). The way to start this user bootloader is described in the Section “Regular Boot Process”, page 7.
4
AT89C51SND1 UART Bootloader
4241B–MP3–07/04
AT89C51SND1 UART Bootloader
Figure 2. Software Boot Vector
UART Bootloader
User Bootloader Application [SBV]00h
FM1
FM0
FLIP Software Program
FLIP is a PC software program running under Windows® 9x//2000/XP, Windows NT® and LINUX® that supports all Atmel Flash microcontrollers. This free software program is available on the Atmel web site.
5
4241B–MP3–07/04
In-System Programming
The ISP allows the user to program or reprogram a microcontroller’s on-chip Flash memory through the serial line without removing it from the system and without the need of a pre-programmed application. This section describes how to start the UART bootloader and the higher level protocol over the serial line.
Bootloader Execution
As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented to allow boot memory to be mapped in the code space for execution at addresses from F000h to FFFFh. The boot memory is enabled by setting the ENBOOT bit in AUXR1. The three ways to set this bit are detailed below. The software way to set ENBOOT consists in writing to AUXR1 from the user’s software. This enables bootloader or API routines execution. The hardware condition is based on the ISP# pin. When driving this pin to low level, the chip reset sets ENBOOT and forces the reset vector to F000h instead of 0000h in order to execute the bootloader software. As shown in Figure 3, the hardware condition always allows In-System recovery when user’s memory has been corrupted.
Software Boot Mapping
Hardware Condition Boot Mapping
Programmed Condition Boot Mapping
The programmed condition is based on the Bootloader Jump Bit (BLJB) in HSB. As shown in Figure 3, this bit is programmed (by hardware or software programming mode), the chip reset set ENBOOT and forces the reset vector to F000h instead of 0000h, in order to execute the bootloader software.
6
AT89C51SND1 UART Bootloader
4241B–MP3–07/04
AT89C51SND1 UART Bootloader
Regular Boot Process Figure 3. Boot Process Algorithm
RESET
Hard Cond? ISP# = L?
Hardware Process
Prog Cond? BLJB = P?
Hard Cond Init ENBOOT = 1 PC = F000h FCON = 00h
Standard Init ENBOOT = 0 PC = 0000h FCON = F0h
Prog Cond Init ENBOOT = 1 PC = F000h FCON = F0h
Hard Init? FCON = 00h?
Software Process
User Boot? SBV < F0h?
User’s Application
User’s Bootloader
Atmel’s Bootloader
7
4241B–MP3–07/04
Physical Layer
The UART used to transmit information has the following configuration: • • • • • Character: 8-bit data Parity: none Stop: 1 bit Flow control: none Baud rate: auto baud is performed by the bootloader to compute the baud rate chosen by the host.
Frame Description
The Serial Protocol is based on the Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized in Table 4. Table 4. Intel Hex Type Frame
Record Mark ‘:’ 1 byte Record length 1 byte Load Offset 2 bytes Record Type 1 byte Data or Info n byte Checksum 1 byte
• •
Record Mark: – – Record Mark is the start of frame. This field must contain “:”. Record length specifies the number of Bytes of information or data which follows the Record Type field. Load Offset specifies the 16-bit starting load offset of the data Bytes, therefore this field is used only for Data Program Record. Record Type specifies the command type. This field is used to interpret the remaining information within the frame. Data/Info is a variable length field. It consists of zero or more Bytes encoded as pairs of hexadecimal digits. The meaning of data depends on the Record Type. The two’s complement of the 8-bit Bytes that
