Single-Chip Microcontroller with MP3 Decoder and Man-Machine Interface

Features • MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volume Control on Left and Right Channels (Software Control Using 31 Steps) – Bass, Medium, and Treble Control (31 Steps) – Bass Boost Sound Effect – Ancillary Data Extraction – “CRC Error” and “MPEG Frame Synchronization” Indicators • Programmable Audio Output for Interfacing With Common Audio DAC – PCM Format Compatible – I2S Format Compatible • 8-bit MCU C51 Core Based (F MAX = 20 MHz) • 2304 Bytes of Internal RAM • 64K Bytes of Code Memory – Flash: AT89C51SND1C, ROM: AT83C51SND1C • 4K Bytes of Boot Flash Memory (AT89C51SND1C) – ISP: Download from USB or UART to Any External Memory Cards • USB Rev 1.1 Controller – “Full Speed” Data Transmission • Built-in PLL – MP3 Audio Clocks – USB Clock • MultiMedia Card™ Interface Compatibility • Atmel DataFlash ® SPI Interface Compatibility • IDE/ATAPI Interface •2 Channels 10-bit ADC, 8 kHz (8-True Bit) – Battery Voltage Monitoring – Voice Recording Controlled by Software • Up to 44 bits of General-purpose I/Os: – 4-bit Interrupt Keyboard Port for a 4 x n Matrix – SmartMedia™ Software Interface • Standard Two 16-bit Timers/Counters • Hardware Watchdog Timer • Standard Full Duplex UART with Baud Rate Generator • Two Wire Interface (TWI) Master and Slave Modes Controller • SPI Master and Slave Modes Controller • Power Management – Power-on Reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode • Operating Conditions: – 3V, ±10%, 25 mA Typical Operating at 25°C – Temperature Range: -40°C to +85°C • Packages – TQFP80, PLCC84 (Development Board) – Dice Single-Chip Microcontroller with MP3 Decoder and Man-Machine Interface AT83C51SND1C AT89C51SND1C Preliminary Summary Description The AT8xC51SND1C are fully integrated stand-alone hardwired MPEG I/II-Layer 3 decoders with a C51 microcontroller core handling data flow and MP3-player control. The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash Memory. Rev. 4106F–8051–10/02 The AT83C51SND1C includes 64K Bytes of ROM memory. The AT8xC51SND1C includes 2304 Bytes of RAM memory. The AT8xC51SND1C provides all necessary features for man machine interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards). Typical Applications • • • • MP3 Player PDA, Camera, Mobile Phone MP3 Car Audio/Multimedia MP3 Home Audio/Multimedia MP3 2 AT8xC51SND1C 4106F–8051–10/02 AT8xC51SND1C Pin Descriptions Figure 1. AT8xC51SND1C, 80-pin TQFP Package P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDD AT89C51SND1C-RO (Flash) AT83C51SND1C-RO (ROM) VDD PVDD FILT PVSS VSS X2 X1 TST UVDD UVSS 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 D+ D- VDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 3 4106F–8051–10/02 Figure 2. AT8xC51SND1C 84-pin PLCC Package(1) P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 VDD NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD PAVDD FILT PAVSS VSS X2 NC X1 AT89C51SND1C-SR (Flash) VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS TST UVDD UVSS VDD Note: 1. Only samples for development board. Pin Descriptions All AT8xC51SND1C signals are detailed by functionality in Table 1 through Table 14. Table 1. Ports Signal Description Signal Name Type Description Port 0 P0 is an 8-bit open-drain bi-directional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS . Port 1 P1 is an 8-bit bi-directional I/O port with internal pull-ups. Alternate Function VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 NC D+ D- VDD 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 P0.7:0 I/O AD7:0 P1.7:0 I/O KIN3:0 SCL SDA 4 AT8xC51SND1C 4106F–8051–10/02 AT8xC51SND1C Table 1. Ports Signal Description (Continued) Signal Name P2.7:0 Type I/O Description Port 2 P2 is an 8-bit bi-directional I/O port with internal pull-ups. Alternate Function A15:8 RXD TXD P3.7:0 I/O Port 3 P3 is an 8-bit bi-directional I/O port with internal pull-ups. INT0 INT1 T0 T1 WR RD MISO MOSI SCK SS - P4.7:0 I/O Port 4 P4 is an 8-bit bi-directional I/O port with internal pull-ups. P5.3:0 I/O Port 5 P5 is a 4-bit bi-directional I/O port with internal pull-ups. Table 2. Clock Signal Description Signal Name Type Description Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected. PLL low pass filter input FILT receives the RC network of the PLL low pass filter. Alternate Function X1 I - X2 O - FILT I - Table 3. Timer 0 and Timer 1 Signal Description Signal Name Type Description Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set by a low level on INT0. Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level on INT1. P3.3 P3.2 Alternate Function 5 4106F–8051–10/02 Table 3. Timer 0 and Timer 1 Signal Description (Continued) Signal Name Type Description Timer 0 External Clock Input When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer 1 External Clock Input When Timer 1 operates as a counter, a falling edge on the T1 pin increments the count. Alternate Function T0 I P3.4 T1 I P3.5 Table 4. Audio Interface Signal Description Signal Name DCLK DOUT DSEL Type O O O Description DAC Data Bit Clock DAC Audio Data DAC Channel Select Signal DSEL is the sample rate clock output. DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). Alternate Function - SCLK O - Table 5. USB Controller Signal Description Signal Name Type Description USB Positive Data Upstream Port This pin requires an external 1.5 kΩ pull-up to VDD for full speed operation. USB Negative Data Upstream Port Alternate Function D+ I/O - D- I/O - Table 6. MutiMediaCard Interface Signal Description Signal Name MCLK Type O Description MMC Clock output Data or command clock transfer. MMC Command line bi-directional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. MMC Data line bi-directional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to VDD or VSS. Alternate Function - MCMD I/O - MDAT I/O - 6 AT8xC51SND1C 4106F–8051–10/02 AT8xC51SND1C Table 7. UART Signal Description Signal Name Type Description Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. Alternate Function RXD I/O P3.0 TXD O P3.1 Table 8. SPI Controller Signal Description Signal Name Type Description SPI Master Input Slave Output Data Line When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. SPI Master Output Slave Input Data Line When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. SPI Clock Line When in master mode, SCK outputs clock to the slave peripheral. When in slave mode, SCK receives clock from the master controller. SPI Slave Select Line When in controlled slave mode, SS enables the slave mode. Alternate Function MISO I/O P4.0 MOSI I/O P4.1 SCK I/O P4.2 SS I P4.3 Table 9. TWI Controller Signal Description Signal Name Type Description TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the maste