8-bit Microcontroller

Features • 80C51 Core – 12 or 6 Clocks per Instruction (X1 and X2 Modes) – 256 Bytes Scratchpad RAM – Dual Data Pointer – Two 16-bit Timer/Counters: T0 and T1 T83C5121 with 16 Kbytes Mask ROM T85C5121 with 16 Kbytes Code RAM T89C5121 with 16 Kbytes Code RAM and 16 Kbytes EEPROM On-chip Expanded RAM (XRAM): 256 Bytes Versatile Host Serial Interface – Full-duplex Enhanced UART (EUART) with Dedicated Baud Rate Generator (BRG): Most Standard Speeds up to 230K bits/s at 7.36 MHz – Output Enable Input – Multiple Logic Level Shifters Options (1.8V to V CC) – Automatic Level Shifter Option Multi-protocol Smart Card Interface – Certified with Dedicated Firmware According to ISO 7816, EMV2000, GIE-CB, GSM 11.12V and WHQL Standards – Asynchronous Protocols T = 0 and T = 1 with Direct and Inverse Modes – Baud Rate Generator Supporting All ISO7816 Speeds up to D = 32/F = 372 – Parity Error Detection and Indication – Automatic Character Repetition on Parity Errors – Programmable Timeout Detection – Card Clock Stop High or Low for Card Power-down Mode – Support Synchronous Card with C4 and C8 Programmable Outputs – Card Detection and Automatic De-activation Sequence – Step-up/down Converter with Programmable Voltage Output: 5V, 3V (± 8% at 60 mA) and 1.8V (±8% at 20 mA) – Direct Connection to Smart Card Terminals: www.DataSheet4U.com Short Circuit Current Limitation Logic Level Shifters 4 kV ESD Protection (MIL/STD 833 Class 3) Alternate Card Support with CLK, I/O and RST According to GSM 11.12V Standard 2x I/O Ports: 6 I/O Port1 and 8 I/O Port3 2x LED Outputs with Programmable Current Sources: 2, 4, or 10 mA Hardware Watchdog Reset Output Includes – Hardware Watchdog Reset – Power-on Reset (POR) – Power-fail Detector (PFD) 4-level Priority Interrupt System with 7 Sources 7.36 to 16 MHz On-chip Oscillator with Clock Prescaler Absolute CPU Maximal Frequency: 16 MHz in X1 mode, 8MHz in X2 mode Idle and Power-down Modes Voltage Operation: 2.85V to 5.4V Low Power Consumption – 8 mA Operating Current (at 5.4V and 3.68 MHz) – 150 mA Maximum Current with Smart Card Power-on (at 16 MHz X1 Mode) – 30 μA Maximum Power-down Current at 3.0V (without Smart Card) – 100 μA Maximum Power-down Current at 5.4V (without Smart Card) Temperature Range – Commercial: 0 to +70°C Operating Temperature – Industrial: -40 to +85°C Operating Temperature Packages – SSOP24 – QFN32 – PLCC52 • • • • • • 8-bit Microcontroller with Multiprotocol Smart Card Interface T83C5121 T85C5121 T89C5121 AT83C5121 AT85C5121 AT89C5121 • • • • • • • • • • • • • Rev. 4164G–SCR–07/06 Description T8xC5121 is a high performance CMOS ROM/CRAM derivative of the 80C51 CMOS single chip 8-bit microcontrollers. T8xC5121 retains the features of the Atmel 80C51 with extended ROM capacity (16 Kbytes), 512 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1), a full duplex enhanced UART (EUART) with baud rate generator (BRG) and an on-chip oscillator. In addition, the T8xC5121 have, a Multi protocol Smart Card Interface, a dual data pointer, 2 programmable LED current sources (2-4-10 mA) and a hardware Watchdog. T89C5121 Flash RAM version and T85C5121 Code RAM version can be loaded by InSystem Programming (ISP) software residing in the on-chip ROM from a low-cost external serial EEPROM or from R232 interface. T8xC5121 have 2 software-selectable modes of reduced activity for further reduction in power consumption. Block Diagram Figure 1. Block Diagram EVCC CVSS DVCC RxD TxD VSS VCC (2) (2) XTAL1 XTAL2 Xtal Osc (3) EUART BRG DC/DC XRAM 256 x8 LI RAM 256 x8 ROM 16K x8 CRAM 16K x8 Voltage Reg. Converter CV CC (1) CC4 (1) CC8 (1) CIO (1) CRST (1) CCLK (1) CPRES (2) CIO1 (2) CRST1 (2) CCLK1 :1-16 Clock Prescaler C51 CORE IB-bus SCIB Level Shifters CPU X2 EA PSEN ALE (4) Timer 0 Timer 1 INT Ctrl 6 I/Os Watchdog POR PFD 8 I/Os Parallel I/O Ports Direct Drive LED Output Alternate Card (2) (2) P2 P0 (2) (2) RST (2) (2) LED0 LED1 P3 T0 T1 INT0 Notes: 1. 2. 3. 4. Alternate function of Port 1 Alternate function of Port 3 Only for the Code RAM version Only for PLCC52 (1): 2 A/T8xC5121 4164G–SCR–07/06 INT1 P1 A/T8xC5121 Pin Description Figure 2. 24-pin SSOP Pinout CVSS LI CVCC P1.5/CRST P1.4/CCLK P1.3/CC4 P1.2/CPRES P1.1/CC8 P1.0/CIO RST XTAL2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC EV CC DVCC VSS P3.0/RxD P3.1/TxD P3.3/INT1/OE P3.4/T0 P3.2/INT0 P3.5/CIO1/T1 P3.6/CCLK1/LED0 P3.7/CRST1/LED1 XTAL1 Figure 3. QFN32 Pinout CVss Vcc EVcc DVcc N/C LI N/C 32 31 30 29 28 27 26 25 CVcc P1.5/CRST P1.4/CCLK P1.3/CC4 P1.2/CPRES P1.1/CC8 P1.0/CIO RST N/C 1 2 3 4 5 6 7 8 N/C QFN32 24 23 22 21 20 19 18 17 Vss Vss P3.0/RxD P3.1/TxD P3.3/INT1/OE P3.4/T0 P3.2/INT0 P3.5/CIO1/T1 9 10 11 12 13 14 15 16 P3.7/CRST1/LED1 P3.6/CCLK1/LED0 N/C N/C XTAL2 XTAL1 N/C 3 4164G–SCR–07/06 Figure 4. PLCC52 Pinout P1.5/CRST CVCC CVSS VCC EVCC NC NC NC NC NC 7 P1.4/CCLK P1.3/CC4 EA PSEN ALE P2.7/A15 P2.6/A14 P2.5/A13 P1.2/CPRES P1.1/CC8 P1.0/CIO P2.4/A12 RST 8 9 10 11 12 13 14 15 16 17 18 19 20 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 DV CC VSS P3.0/RxD P3.1/TxD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.6/AD6 P3.3/INT1/OE P3.4/T0 P3.2/INT0 P3.5/CIO1/T1 21 22 23 24 25 26 27 28 29 30 31 32 33 XTAL2 XTAL1 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P3.7/CRST1/LED1 P0.5/AD5 P3.6/CCLK1/LED0 P0.4/AD4 VCC VSS LI NC 4 A/T8xC5121 4164G–SCR–07/06 P0.7/AD7 NC A/T8xC5121 Signals Table 1. Ports Description Internal Port P1.0 Signal Name CIO Power Alternate Supply CVCC ESD 4 kV Type I/O Description Smart card interface function Card I/O. Input/Output function P1.0 is a bi-directional I/O port . Reset configuration Input . Smart card interface function Card contact 8 Output function P1.1 is a Push-pull port. Reset configuration Input Smart card interface function Card presence Input/Output function I/O P1.2 is a bi-directional I/O port with internal pull-ups- ( External Pull-up configuration can be selected). Reset configuration Input (high level due to internal pull-up) Smart card interface function Card contact 4 Output function P1.3 is a Push-pull port. Reset configuration Input (high level due to internal pull-up) Smart card interface function Card clock Input/Output function P1.4 is a a Push-pull port. Reset configuration Output at low level Smart card interface function Card reset Input/Output function P1.5 is a a Push-pull port. Reset configuration Output at low level All the T8xC5121 signals are detailed in Table 1. The port structure is described in Section “Port Structure Description”. I/O I P1.1 CC8 CVCC 4 kV O O I P1.2 CPRES VCC 4 kV I I P1.3 CC4 CVCC 4 kV O O I P1.4 CCLK CVCC 4 kV O I/O O P1.5 CRST CVCC 4 kV O I/O O 5 4164G–SCR–07/06 Table 1. Ports Description (Continued) Internal Port P3.0 Signal Name RxD Power Alternate Supply EVCC ESD Type I Description UART function Receive data input Input/Output function P3.0 is a bi-directional I/O port with internal pull-ups. Reset configuration Input (high level) UART function P3.1 TxD EVCC O Transmit data output OE active at low or high level depending of PMSOEN bits in SIOCON Reg. I/O Input/Output function P3.1 is a bi-directional I/O port with internal pull-ups. Reset configuration High impedance due to PMOS switched OFF External interrupt 0 P3.2 INT0 DVCC I INT0 input set IE0 in the TCON register. If bit IT0 in this register is set, bits IE0 are set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by a low level on INT0. Input/Output function P3.2 is a bi-directional I/O port with internal pull-ups. Timer 0: Gate input I INT0 serves as external run control for Timer 0 when selected in TCON register. I Reset configuration Input (high level) External Interrupt 1 P3.3 INT1 OE EVCC I INT1 input set OEIT in ISEL Register, IE1 in the TCON register. If bit IT1 in this register is set, bits OEIT and IE1 are set by a falling edge on INT1. If bit IT1 is cleared, bits OEIT and IE1 is set by a low level on INT1 UART function I Output enable. A low or high level (depending OELEV bit in ISEL Register) on this pin disables the PMOS transistors of TxD (P3.1) and T0 (P3.4). This function can be disabled by software I/O Input/Output function P3.3 is a bi-directional I/O port with internal pull-ups. Timer 1 function: Gate input I INT1 serves as external run control for Timer 1 when selected in TCON register. I Reset configuration Input (high level) UART function P3.4 T0 EVCC O OE active at low or high level depending of PMSOEN bits in SIOCON Reg. I/O I Z I/O 6 A/T8xC5121 4164G–SCR–07/06 A/T8xC5121 Table 1. Ports Description (Continued) Internal Port Signal Name Power Alternate Supply ESD Type I/O Description Input/Output function P3.4 is a bi-directional I/O port with internal pull-ups. Timer 0 function: External clock input I When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Z Reset configuration High impedance due to PMOS switched OFF Alternate card function Card I/O Input/Output function P3.5 is a bi-directional I/O port with internal pull-ups. Timer 1 function: External clock input I When Timer 1 operates as a counter, a falling edge on the T1 pin increments the count. I Reset configuration Input (high level due to internal pull-up) Alternate card function Card clock LED function These pins can be directly connected to the cathode of standard O LED without external current limiting resistors. The typical current of each output can be programmed by software to 2, 4 or 10 mA (LEDCON register). I/O Input/Output function P3.6 is a LED port. Reset configuration Input at high level Alternate card function Card reset LED function These pins can be directly connected to the cathode of standard LED without external current