Transceiver

Data Demodulation and Crystal Selection for the AT86RF211S 1. Introduction This document gives an overview of the receiver chain of the AT86RF211S and its associated embedded features: • Discriminator: Demodulation of the RF signal (principle, measurement/tuning of output voltage) • Data slicer:From analog to digital world (different modes of functioning, how to set up the data slicer threshold) It also emphasizes the new possibilities of the AT86RF211S • Selection of lower cost crystal • Data rate up to 128 kbps • Frequency deviation wider than ±100 kHz AT86RF211S FSK Transceiver for ISM Radio Applications Application Note 2. From Analog to Digital 2.1 Demodulation www.DataSheet4U.com 2.1.1 Principle The FSK modulation used by the AT86RF211S consists in coding each bit as follows: • “0”: transmission of an RF signal at a frequency F0 • “1”: transmission of an RF signal at a frequency F1 • The channel frequency (or carrier) is the middle frequency Fc = (F0 + F1)/2 • F1 - Fc = Fc - F0 is called the frequency deviation The receiver therefore has the overall task to: • Down-convert the signal at lower frequencies (for filtering purposes): 10.7 MHz and 455 kHz • Convert the frequencies into voltages (= discriminator) • Make a decision to separate “0” from “1” levels (= data slicer) Rev. 5418A–WIRE–04/05 Figure 2-1. Principle of Demodulation Signal down-converted at 10.7 MHz 2 nd down-conversion at 455 kHz Vcc 1st filtering stage FRF 2nd filtering stage Discriminator FV Converter GND L01 L02 10.7 MHz bandwidth = hundreds of kHz 455 kHz bandwidth = tens of kHz SYNCHRONOUS RESHAPED CMOS LEVELS Vcc DATAMSG GND Data slicer threshold DATACLK CLOCK RECOVERY Embedded function The AT86RF211S discriminator is analog: the output voltage is proportional to the input frequency. It was particularly designed to accept a very long sequence of “zeros” or “ones” (i.e. a constant input frequency). This is not the case for all receivers (in other words, with some transceivers it is necessary to use DC-free data encoding). Figure 2-2. Classic Discriminator without DC Ability 0 1 0 1 1 0 Sequence 1 0 2 AT86RF211S Application Note 5418A–WIRE–04/05 AT86RF211S Application Note Figure 2-3. AT86RF211: Discriminator with DC Ability 0 1 0 1 10 Sequence 1 2.1.2 Standard/Narrowband Modes of the Discriminator Since the output swing of the discriminator is proportional to the input frequency deviation, small frequency deviations (used in narrowband applications) lead to smaller peak-to-peak values of discriminator output. For this reason, the discriminator’s gain can be selected. The AT86RF211S features four different gains – NDB, SDB, MDB and WDB – where NDB and SDB are fully compatible with the AT86RF211. The slope of the demodulator is: • Standard Discriminator Bandwidth mode: 14 mV/kHz at 2.4V (+5 mV per volt of power supply) • Narrow Discriminator Bandwidth mode: 28 mV/kHz at 2.4V (+10 mV per volt of power supply) • Medium Discriminator Bandwidth mode: 9 mV/kHz at 2.4V (+4 mV per volt of power supply) • Wide Discriminator Bandwidth mode: 5.5 mV/kHz at 2.4V (+2 mV per volt of power supply) 2.1.3 System Requirements In order for the system to operate properly, the basic requirements are the following: • The frequency deviation must be in accordance with the data rate (the higher the data rate, the larger the frequency deviation). • The down-converted frequencies must remain within the IF filters over the entire operating conditions (temperature range, ageing), particularly when a narrow IF2 filter is used. The typical values are: => 10.7 MHz filter: ±50 to ±150 kHz (ceramic filter) => optional 455 kHz second IF filter: ±2 to ±17.5 kHz (ceramic filter). • The output of the discriminator must not exceed the maximum allowed voltage range. The level on DISCOUT depends on several parameters: the received signal frequency, the receiver local oscillator, the amplifier offsets, etc. Important Notes: • The temperature drifts of the crystal are often given in ppm (parts per million) over a given temperature range. 1 ppm is 0.9 kHz at 900 MHz and 0.4 kHz at 400 MHz, with a 10.245 MHz crystal. 3 5418A–WIRE–04/05 • The crystal specifications in this document (ageing and temperature drifts) are given for the 868 to 915 MHz bands. For an application in the 400 MHz to 480 MHz band, these specifications can be relaxed and multiplied by 2. • These specifications (temperature and ageing) include the Tx and Rx sides: the overall drift must meet these requirements. • Thanks to the high resolution of the AT86RF211S synthesizer (typically 200 Hz) a given accuracy can be achieved by software: a small shift of the frequency (made by software) is able to compensate a temperature or ageing drift with no additional hardware cost. 2.2 Data Slicing Once the frequency has been converted into a voltage, a decision must be made to identify the “0” and “1” levels and convert them into CMOS levels. This is achieved thanks to a comparator. The AT86RF211S offers two data-slicing possibilities. Figure 2-4. Data Slicing Data slicer threshold set on SKFILT pin Data slicing options Demodulated signal on DISCOUT pin Data slicer threshold level set by internal DAC (DSREF) With the AT86RF211S, a hold is possible on the SKFILT capacitor. This helps to maintain the average value of the signal captured without any discharge during reception of the message. 2.2.1 External Mode Comparing The Signal to its Average Value A first possibility consists in comparing the signal to its own average value: a capacitor on SKFILT (pin 25) is charged to the average value of the signal. 4 AT86RF211S Application Note 5418A–WIRE–04/05 AT86RF211S Application Note Figure 2-5. Demodulator Output (DSIN) “External” Comparison Mode: Signal Compared to its Average Value. + 0 1 Data Slicer + A 100K Data Slicer Threshold DATAMSG DAC B SKFILT The value of the capacitor is a trade-off: it must be low enough to make the charging time as short as possible, but high enough to “memorize” the level during the length of the maximum number of similar consecutive bits. The lower the data rate, the higher the capacitor. Practical values are: • Data rate = 2400 bps => C = 22 nF • Data rate = 4800 bps => C = 10 nF • Data rate = 9600 bps => C = 4.7 nF • Data rate ≥ 19200 bps => C = 2.2 nF This procedure makes it impossible to receive a signal containing a DC component (= a long sequence of “0” or “1”): the signal and data slicer thresholds become very close to one another and the decision can no longer be made. Therefore, an adequate data encoding technique must be used to prevent any DC component. Manchester encoding is a popular way of preventing the existence of any DC component. It consists in encoding the data as follows: – Logical “0”: 01 – Logical “1”: 10 This way, a long sequence of “0s” will be transformed into a “0101010101…” sequence. A maximum of two similar successive low or high levels can be seen. Note: Many other DC-free data encoding techniques are possible that increase the effectiveness of the encoding, but the principle of operation is the same. Thanks to the new “Charge & Hold” feature of the AT86RF211S, it is possible to suppress message encoding. A dedicated application note entitled “Benefits of Charge & Hold” reference 5420, is available that details this. 5 5418A–WIRE–04/05 2.2.2 Internal Mode Comparing the Signal to a Fixed Level A second possibility consists in comparing the signal to a fixed threshold (that does not depend on the signal itself). This is a very powerful mode: it enables you to take advantage of the receiver’s full bandwidth without need for a preamble (the first bit can be data sliced correctly and processed by the microcontroller). Figure 2-6. Internal Comparison Mode: Signal Compared to a Fixed Level DISCOUT + - DATAMSG + - Signal + - DSIN Fixed threshold (internally set up by software, DTR[5:2]) In this mode, the system designer must make sure that the data slicer threshold is tuned close to the middle of the demodulated signal. Figure 2-7. DISCOUT: demodulated data “Internal” Comparison Mode Not OK Comparator threshold OK Time Notes: 1. If an active low-pass filter with a transistor (Sallen-Key for instance) is inserted between DISCOUT and DSIN, the internal comparison mode must be avoided as the Vbe offsets the demodulated signal out of the data slicer window. The use of an op. amp. does not offset and the signal thereafter is allowed for active filtering. 2. It is recommended to use a simple R/C low-pass filter instead of an active one. 2.2.3 2.2.3.1 Manchester vs. NRZ Manchester • The frequency spectrum is uniform (same number of “0” and “1” frequencies). • The demodulator can be simple (no DC level). • Data slicing is very easy (the default threshold is at the middle of the demodulated signal). • A preamble to charge the capacitor to a correct value is required. • Two transitions are required to send one bit. Since the number of transitions per second is limited by the hardware, the number of “useful” bits is divided by two. For instance, with 128 000 transitions per second allowed by the AT86RF211S, 64 000 useful bits can be transmitted in this mode. 6 AT86RF211S Application Note 5418A–WIRE–04/05 AT86RF211S Application Note 2.2.3.2 NRZ • Enhanced encoding effectiveness. • If the internal mode is used: – there is no need for a preamble once the threshold is properly set-up (the first bit can be demodulated). – 128 000 transitions per second = 128 000 useful bits. – the threshold must be tuned (this can be done automatically through the software). • If the external mode is used: – the Hold mode grants the data slicer long streams of ‘0’ and ‘1’. – there is a need for a pream