Features
• • • • • • • • • •
850–930 MHz Output Frequency Rx Current: 14.5 mA Low Sleep Mode Current: 1 uA DSSS Processing and BPSK Modulation/Demodulation Battery Voltage Monitoring Circuitry 4 mW (6 dBm) Min. Transmit Power @ Vdd = 1.8V Serial Peripheral Interface (SPI) Control Power Supply Voltage Operating Range: 1.8V to 3.6V Low External Component Count 48QFN Package
Applications
• • • • • •
Low Band IEEE 802.15.4/ZigBee™-based Systems Industrial, Commercial, Home Lighting Control, Security, and HVAC Inventory Management Health Monitoring Wireless PC Peripherals such as Mouse, Keyboard, and Joystick Consumer Electronics Remote Controls and Toys
AT86RF210 Z-Link™ Transceiver
868/902–928 MHz Direct Sequence Spread Spectrum BPSK Transceiver Preliminary
Description
The Atmel AT86RF210 Z-Link ™ Transceiver is a fully integated, low-cost ZigBee™ transceiver capable of transmitting and receiving BPSK modulated digital data over a frequency range of 868 MHz and 902–928 MHz using a minimum number of external components. It combines excellent RF performance with low cost, small size and low current consumption. The AT86RF210 includes a crystal stabilized Fractional-N synwww.DataSheet4U.com thesizer, BPSK transmitter and receiver, and full Direct Sequence Spread Spectrum Signal (DSSS) processing, including spreading and despreading. The device is fully compatable with IEEE 802.15.4 and ZigBee standards. It includes internal voltage regulation and battery monitoring circuitry and requires a minimum number of external support components. Figure 1. Block Diagram
Low Noise I/Q Mixer Amp Rx In Sw Out Ant In Sw In Tx Out Power Amp Data In Modulator Spreader SPI Bus SDO SDI SCLK SEL T/R Switch Synthesizer Despreader Data Out IF Amp Polyphase Filter Demodulator
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Figure 1. Functional Block Diagram
LNAOUT GND VDDA VSSA VDDD VSSD Reg Filter RSSI TEST RXD
Lim/PPF DC DIST
Despreader
SUB P P F M U X 1 Image Reject Filter P P F M U X 2 IQ-Limiter Strip 1.2 MHz CCA
LNAIN
LNA
BPSK Demod
1.200 MHz
LNAVSS RSWOUT VSS ANT VSS TSWIN FSK TUNE LOGIC
START
bandwidth Control Low Voltage Detect POR TXD
TR SW
/2 with Buffers
PPF AUTOCAL Circuit
VDD DBLR
NC
DC DIST/BG/PTAT with main BandGAP /N-M
VCO Fcx2
CHP_RDY S T A T U S
VSS PA OUT
PA
Fine Atten
PRGM DIV
Coarse Lock/Lock Detect Phase Detector Clock Distribution
Mode Logic
RESET_ RX TX CLK SEL
VSS BPSKO OK MOD
SDMOD
Tune Word
PA Regulator
FROM TXD
Cap Array
Spreader
Charge Pump
Xstal Osc
Serial Configruation Register
SCL SDO
PAREG
VCOREG
VCO
NC
NC
VCO VCO CPVCO CPOUT VSS TUNE
XTALGND
XTAL1
XTAL2
SDI
Table 1. Absolute Maximum Ratings*
Storage Temperature ..............................................−65 to +150 Maximum Input Voltage...........................................VDD + 0.5V Maximum Operating Voltage (VDD ) ................................... 4,5 *NOTE: Stresses beyond those listed in this table may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Operating Conditions
Symbol TAMB VSUPPLY HUMIDITY Note: Parameter Operating temperature Voltage supply range Humidity Min −40 1.8 10 2.7 Typ Max 85 3.6 90 Unit °C V %
Unit operation is guaranteed by design when operating within these ranges.
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Table 3. DC Characteristics
Symbol IDDRX IDDTX IDDSleep VPOR VIH VIL VOH VOL Parameter Supply current, receive mode Supply current, transmit mode VDD = 3.3V Supply current, sleep mode Power-on reset voltage Digital input voltage high Digital input voltage low Digital output voltage high Digital output voltage low 0.7*VDD 0.3*VDD 0.7*VDD 0.3*VDD Min Typ 14.5 60 1 1.5 Max Unit mA mA uA V V V V V
Table 4. Receiver AC Characteristics
Symbol FLO ZRF Rx Sens Rx NF Rx P1dB Rx IP3 Rx LO Leakage Pin EDthresh Ttx/rx Trx/tx RJAMadj RJAMalt IFCF IFBW Imreg RX IFS/N Rx DR RSSI GN RSSI RG Parameter Local oscillator operating range, external inductor Port impedance antenna input Sensitivity, PER = 1% 40 kB/s, BW = 600 kHz BPSK modulation Receiver noise figure Receiver input 1dB compression point LNA gain max setting Input IP3 Receiver LO leakage (all possible paths) Maximum input signal; LNA gain min setting Default energy detection threshold (programmable) Turnaround time, transmit to receive Turnaround time, receive to transmit Receiver relative jamming resistance adjacent channel (desired signal = −89 dBm) Receiver relative jamming resistance alternate channel (desired signal = −89 dBm) IF center frequency IF bandwidth IF image rejection RX IF SNR (600 KHz BW) Min input signal = −100 dBm Receiver max data rate RSSI Gain RSSI RANGE −105 0 30 1.2 600 −35 10 40 1.0 −30 −84 100 100 Min 850 50 −95 6.0 −40 −30 −80 −20 Typ Max 930 Unit MHz Ohm dBm dB dBm dBm dBm dBm dBm usec usec dB dB MHz KHz dB dB Kb/s uA/dB dBm
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Table 5. Transmitter AC Characteristics
Symbol Tx Pout Parameter Transmitter output power: Vdd = 1.8V Vdd = 3.6V Tx symbol rate 915 MHz band Tx symbol rate 868 MHz band Transmit error vector magnitude measured over 1000 chips Transmit power spectral density 915 MHz band; |f–fc| >1.2 MHz (absolute measured in 100 KHz resolution BW) Transmitter power variation over temperature Antenna switch impedance Transmit spurious within ±2 MHz Transmit spurious beyond ±2 MHz Transmitter power control resolution Transmitter power control range Transmitter low-voltage threshold Transmitter low-voltage output power Transmitter turn-on time 90% full power Transmitter turn-off time less than 10% of output power 1.8 0.25 10 10 0.25 25 1.9 0.50 3 50 −25 −35 0.75 40 20 35% −20 dBm Min Typ 6 12 Kbit/s Kbit/s Max Unit dBm
Rsym Rsym EVM PSD
Tx Pvar Tx/Rx Z Tx spur Tx spur Tx Pcon Tx Pran Tx lvt Tx lvpo Tx tot Tx tofft
dB Ohm dBc dBc dB dB Volt mwatt usec usec
Table 6. Synthesizer AC Characteristics
Symbol F LO LOPN Fpull Lopno TXtal TSynth Synthres Parameter Carrier frequency LO phase noise (integrated 10 Hz–100 KHz rms) Crystal oscillator frequency pulling @ 25°C Local oscillator phase noise 2.0 MHz offset from LO Crystal oscillator settling time Phase locked loop settling time Synthesizer tuning resolution 500 Min 850 6 20 −95 150 100 Typ Max 930 Unit MHz deg ppm dBc usec usec Hz
. Table 7. Serial Configuration Register*
Symbol TRISE TFALL TCLKS Parameter CMOS input rise time CMOS input fall time CLK setup time 25 Min Typ 20 20 Max Unit nsec nsec nsec
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Table 7. Serial Configuration Register* (Continued)
Symbol TCLKH TCLKW TSDIS TSDIH TSDOD Note: Parameter CLK hold time CLK pulse width SDI setup time SDI hold time SDO delay time Min 25 50 25 25 25 Typ Max Unit nsec nsec nsec nsec nsec
*Rise and fall time is measured 10%–90%. Delay, setup, and hold times are measured 50%–50%
Table 8. Low Battery Detector Characteristics
Symbol Lvbat 0 Parameter Low voltage battery detector threshold voltage mode 0 (5 bit resolution) Min 1.5 Typ Max 3.5 Unit Volt
Table 9. Preliminary PIN Description QFN48
PIN SUB LNARFIN LNAVSS RSWOUT VSS ANT VSS TSWIN PAOUT VSS VDDA PAREG VCOVDD VCOREG No Connect No Connect VCOVSS VCOTUNE Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A_I/O A_I V_I A_O V_I V_I NA NA NA NA NA NA NA NA Type V_I/O RF_I RF_I/O RF_I/O RF_I/O RF_I/O RF_I/O RF_I/O RF_I/O Startup Cond GND NA NA NA NA NA NA NA NA Description Substrate connection Low-noise amplifier RF input Analog ground for the LNA Transmit-receive switch out. Signal from ANT is routed through the TR switch to the LNA input. Transmit-receive switch isolation ground 1. Antenna RF input/output. Nominal impedance 50Ω, part of T/R switch. Routes signal to the LNA or from the PA. Transmit-receive switch isolation ground 2. Transmit-receive switch input. Signal from PA comes into TR switch and is routed to ANT. PA signal routed into the T/R switch from the PA. Pin not used Secondary analog power supply input. Set in proximity to power amplifier circuits. PA regulator output. Settable current source output for charging a large external capacitor during battery operation. VCO power supply input External filter cap for the VCO regulator Pin not used Pin not used VCO power supply ground LO VCO control input. An internal differential varactor diode tunes the LO frequency. The control voltage should be referenced to LOGND.
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Table 9. Preliminary PIN Description QFN48 (Continued)
PIN CPOUT CPVSS CPVDD XTAL1 XTAL2 Num 19 20 21 22 23 Type A_I A_I/O V_I A_I A_I Startup Cond NA NA NA NA NA Description Charge pump output Analog synthesizer ground Analog synthesizer power supply Crystal oscillator input 1. One side of oscillator crystal is connected to this pin. Crystal oscillator input 2. When internal oscillator is used, this pin has crystal connected. When external clock is used, the external clock is input on this pin. Crystal oscillator ground Transmit data input from the controller Pin not used Serial data input Input to configuration data shift register. Data accepted at the rising edge of SCL. Output from configuration data shift register. Data changes at the falling edge of SCL. Serial data clock SPI slave select line Clock output to controller. Can be divided by 1 to 16. Mode control input. TX HIGH with RX LOW causes chip to go to transmit. Mode control input. RX HIGH with TX LOW causes chip to go to receive mode. Digital power supply input Digital power supply ground. Oscillator start. A transition on this pin will start the internal oscillator. A low on this pin allows the part to run from an external clock. Chip ready. Handshake signal between the controller and the chip. Also acts a
