Single-Chip Flash Microcontroller

Features • MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volume Control on Left and Right Channels (Software Control using 31 Steps) – Bass, Medium, and Treble Control (31 Steps) – Bass Boost Sound Effect – Ancillary Data Extraction – CRC Error and MPEG Frame Synchronization Indicators 20-bit Stereo Audio DAC – 93 dB SNR playback stereo channel – 32 Ohm/ 20 mW stereo headset drivers – Stereo Line Level Input, Differential Mono Auxiliary Input Programmable Audio Output for Interfacing with External Audio System – PCM Format Compatible – I2S Format Compatible Mono Audio Power Amplifier – 440mW on 8 Ohms Load 8-bit MCU C51 Core Based (F MAX = 20 MHz) 2304 Bytes of Internal RAM 64K Bytes of Code Memory – AT89C51SND2C and 89SND2CMP3B: Flash (100K Erase/Write Cycles) – AT83SND2C and 83SND2CMP3B: ROM 4K Bytes of Boot Flash Memory (AT89C51SND2C and 89SND2CMP3B) – ISP: Download from USB (standard) or UART (option) USB Rev 1.1 Controller – Full Speed Data Transmission Built-in PLL www.DataSheet4U.com – MP3 Audio Clocks – USB Clock MultiMedia Card ® Interface Compatibility Atmel DataFlash ® SPI Interface Compatibility IDE/ATAPI Interface 2 Channels 10-bit ADC 8 kHz (8-true bit) for AT8XSND2CMP3B – Battery Voltage Monitoring – Voice Recording Controller by Software Up to 32 Bits of General-purpose I/Os – 1 Interrupt Keyboard – SmartMedia ® Software Interface 2 Standard 16-bit Timers/Counters Hardware Watchdog Timer Standard Full Duplex UART with Baud Rate Generator Two Wire Master and Slave Modes Controller SPI Master and Slave Modes Controller Power Management – Power-on Reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode Operating Conditions: – 2.7 to 3.6V – Power amplifier supply 3.2V to 5.5V – 37mA Typical Operating at 25°C playing music on earphone – Temperature Range: -40°C to +85°C Packages – CTBGA100 • • • • • • • • • • • • • • • • • • • • Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface AT83SND2C AT89C51SND2C AT80SND2CMP3B AT83SND2CMP3B AT89SND2CMP3B • • 4341F–MP3–03/06 1. Description The AT8xC51SND2C has been developed for handling MP3 ringing tones in mobile phones and can replace sound generators while adding SD/MMC card reader, MP3 music decoding, and connection of the cell phone to a PC through USB. Cell phones can also be used as a thumb drive extending cell phone capabilities. The AT8xC51SND2C are fully integrated stand-alone hardwired MPEG I/II-Layer 3 decoder with a C51 microcontroller core handling data flow, MP3-player control, Stereo Audio DAC and Mono Audio Power Amplifier for speaker control. The AT89C51SND2C includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash memory. The AT83SND2C includes 64K Bytes of ROM memory. The AT8xC51SND2C include 2304 Bytes of RAM memory. The AT8xC51SND2C provides the necessary features for human interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards). The AT8XSND2CMP3B provides also ADC input to the previous configuration. 89SND2CMP3B includes 64K Bytes of Flash memory. 83SND2CMP3B includes 64K Bytes of ROM memory. In the following of the document, AT8xC51SND2C refers to the generic product. When named explicitly, AT8XSND2CMP3B refers to the version with A/D converter. 2. Typical Applications • MP3-Player • PDA, Camera, Mobile Phone MP3 • Car Audio/Multimedia MP3 • Home Audio/Multimedia MP3 2 AT8xC51SND2C/MP3B 4341F–MP3–03/06 AT8xC51SND2C/MP3B 3. Block Diagram Figure 3-1. AT8xC51SND2C / AT8XSND2CMP3B Block Diagram ISP ALE VDD VSS UVDD UVSS FILT X1 X2 RST 3 Clock and PLL Unit C51 (X2 Core) Interrupt Handler Unit INT0 INT1 3 (ADC is available on 8xSND2CMP3B only) 10-bit A to D Converter D+ DAREF AIN1:0 USB Controller I/OPorts IDE Interface MP3 Decoder Unit 8-Bit Internal Bus RAM 2304Bytes Flash ROM 64 KBytes Flash Boot 4 KBytes P0-P4 Keyboard Interface 3 3 KIN0 DOUT DCLK DSEL SCLK I2S/PCM Audio Interface UART and BRG TXD RXD Timers 0/1 Watchdog 3 3 4 4 4 4 T0 T1 HSR HSL AUXP AUXN LINEL LINER MONOP MONON Audio DAC SPI/DataFlash Controller SS MISO MOSI SCK SCL SDA TWI Controller MCLK PAINP PAINN HPP HPN Audio PA MMC Interface MDAT MCMD 3 Alternate function of Port 3 4 Alternate function of Port 4 3 4341F–MP3–03/06 4. Pin Description 4.1 Pinouts Figure 4-1. AT8xC51SND2C 100-pin BGA Package (no ADC) 10 NC 9 NC 8 P2.0/ A8 7 P4.1/ MOSI 6 VDD 5 VSS 4 NC 3 AUXP 2 AUXN 1 ALE A B C D E F G H J K VDD P2.2/ A10 P2.1/ A9 P4.0/ MISO P4.2/ SCK MONON MONOP P0.0/ AD0 KIN0 ISP/ NC P2.4/ A12 P2.3/ A11 P2.5/ A13 P4.3/ SS P0.6/ AD6 P0.4/ AD4 P0.3/ AD3 P0.2/ AD2 P0.1/ AD1 NC P2.6/ A14 P2.7/ A15 MCLK NC P0.7/ AD7 P0.5/ AD5 NC NC NC NC EA VSS VDD ESDVSS VDD SDA AUDVREF SCL HSL AUDVDD MCMD MDAT NC P3.2/ INT0 P3.1/ TXD VSS FILT PVDD HSR HSVDD RST AUDRST SCLK DSEL P3.4/ T0 P3.0/ RXD LINER LINEL PVSS HSVSS NC VSS DOUT DCLK P3.5/ T1 TST X1 X2 INGND AUDVSS VDD AUDVSS CBP LPHN P3.7/ RD P3.6/ WR VSS D- D+ AUDVCM PAINP PAINN HPP AUDVBAT HPN AUDVSS P3.3/ INT1 VDD UVDD UVSS Notes: 1. ISP pin is only available in AT89C51SND2C product. Do not connect this pin on AT83SND2C product. 2. NC is Do Not Connect. 4 AT8xC51SND2C/MP3B 4341F–MP3–03/06 AT8xC51SND2C/MP3B 4.2 Figure 4-2. AT8XSND2CMP3B 100-pin BGA Package (with ADC) 10 P2.2/ A10 9 P2.1/ A9 8 P4.0/ MISO 7 ESDVSS 6 VDD 5 VSS 4 MONON 3 MONOP 2 P0.0/ AD0 1 ALE A B C D E F G H J K P2.3/ A11 P2.4/ A12 P2.0/ A8 P4.2/ SCK P0.7/ AD7 P0.5/ AD5 P0.3/ AD3 AUXP P0.1/ AD1 ISP/ NC VDD P2.5/ A13 P4.1/ MOSI P4.3/ SS P0.6/ AD6 P0.4/ AD4 P0.2/ AD2 AUXN KIN0 AUDVDD VSS P2.6/ A14 P2.7/ A15 SDA NC NC NC NC NC VDD VDD EA FILT CBP HSL AUDVREF AUDVCM HSR SCL HSVDD MCMD MCLK MDAT AIN1 ADCVDD P3.7/ RD TST LINEL PVDD HSVSS SCLK AUDRST RST AIN0 LPHN P3.4/ T0 P3.0/ RXD PVSS LINER VSS DCLK DOUT DSEL ADCV REFP ADCVSS P3.6/ WR P3.1/ TXD X2 INGND AUDVSS VSS PAINP PAINN ADCV REFN P3.3/ INT1 P3.5/ T1 P3.2/ INT0 X1 D+ UVDD ESDVSS AUDVSS HPP AUDVBAT AUDVBAT HPN AUDVSS D- VDD UVSS Notes: 1. ISP pin is only available in 89SND2CMP3B product. Do not connect this pin on 83SND2CMP3B product. 2. NC is Do Not Connect. 5 4341F–MP3–03/06 4.3 Signals All the AT8xC51SND2C and AT8XSND2CMP3B signals are detailed by functionality in Table 41 to Table 14. Table 4-1. Ports Signal Description Signal Name Type Description Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Alternate Function P0.7:0 I/O AD7:0 P2.7:0 I/O A15:8 RXD TXD P3.7:0 I/O Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups. INT0 INT1 T0 T1 WR RD MISO MOSI SCK SS P4.3:0 I/O Port 4 P4 is an 8-bit bidirectional I/O port with internal pull-ups. Table 4-2. Signal Name Clock Signal Description Type Description Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected. PLL Low Pass Filter input FILT receives the RC network of the PLL low pass filter. Alternate Function X1 I - X2 O - FILT I - Table 4-3. Signal Name Timer 0 and Timer 1 Signal Description Type Description Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. Alternate Function INT0 I External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low level on INT0#. P3.2 6 AT8xC51SND2C/MP3B 4341F–MP3–03/06 AT8xC51SND2C/MP3B Signal Name Type Description Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1 is set by a low level on INT1#. Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.3 Alternate Function T0 I P3.4 T1 I P3.5 Table 4-4. Signal Name DCLK DOUT DSEL Audio Interface Signal Description Type O O O Description DAC Data Bit Clock DAC Audio Data Output DAC Channel Select Signal DSEL is the sample rate clock output. DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). Alternate Function - SCLK O - Table 4-5. Signal Name D+ D- USB Controller Signal Description Type I/O I/O Description USB Positive Data Upstream Port This pin requires an external 1.5 KΩ pull-up to VDD for full speed operation. USB Negative Data Upstream Port Alternate Function - Table 4-6. Signal Name MCLK MutiMediaCard Interface Signal Description Type O Description MMC Clock output Data or command clock transfer. MMC Co