Single-Chip Flash Microcontroller

Features • MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volume Control on Left and Right Channels (Software Control using 31 Steps) – Bass, Medium, and Treble Control (31 Steps) – Bass Boost Sound Effect – Ancillary Data Extraction – CRC Error and MPEG Frame Synchronization Indicators Programmable Audio Output for Interfacing with Common Audio DAC – PCM Format Compatible – I2S Format Compatible 8-bit MCU C51 Core Based (FMAX = 20 MHz) 2304 Bytes of Internal RAM 64K Bytes of Code Memory – AT89C51SND1C: Flash (100K Erase/Write Cycles) – AT83SND1C: ROM 4K Bytes of Boot Flash Memory (AT89C51SND1C) – ISP: Download from USB (standard) or UART (option) External Code Memory – AT80C51SND1C: ROMless USB Rev 1.1 Controller – Full Speed Data Transmission Built-in PLL – MP3 Audio Clocks – USB Clock MultiMedia Card® Interface Compatibility Atmel DataFlash® SPI Interface Compatibility www.DataSheet4U.com IDE/ATAPI Interface 2 Channels 10-bit ADC, 8 kHz (8-true bit) – Battery Voltage Monitoring – Voice Recording Controlled by Software Up to 44 Bits of General-purpose I/Os – 4-bit Interrupt Keyboard Port for a 4 x n Matrix – SmartMedia® Software Interface 2 Standard 16-bit Timers/Counters Hardware Watchdog Timer Standard Full Duplex UART with Baud Rate Generator Two Wire Master and Slave Modes Controller SPI Master and Slave Modes Controller Power Management – Power-on Reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode Operating Conditions: – 3V, ±10%, 25 mA Typical Operating at 25°C – Temperature Range: -40°C to +85°C Packages – TQFP80, BGA81, PLCC84 (Development Board) – Dice • • • • • • • • • • • • • • • • • • • Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface AT83SND1C AT89C51SND1C AT80C51SND1C • • 4109JS–8051–10/06 1. Description The AT8xC51SND1C are fully integrated stand-alone hardwired MPEG I/II-Layer 3 decoder with a C51 microcontroller core handling data flow and MP3-player control. The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash memory. The AT83SND1C includes 64K Bytes of ROM memory. The AT80C51SND1C does not include any code memory. The AT8xC51SND1C include 2304 Bytes of RAM memory. The AT8xC51SND1C provides the necessary features for human interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards). 2. Typical Applications • • • • MP3-Player PDA, Camera, Mobile Phone MP3 Car Audio/Multimedia MP3 Home Audio/Multimedia MP3 3. Block Diagram Figure 3-1. AT8xC51SND1C Block Diagram INT0 INT1 VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD T0 T1 SS MISO MOSI SCK SCL SDA 3 3 Interrupt Handler Unit Flash ROM 64 KBytes Flash Boot 4 KBytes 3 3 3 3 4 4 4 4 1 1 RAM 2304 Bytes 10-bit A to D Converter UART and BRG Timers 0/1 Watchdog SPI/DataFlash Controller TWI Controller C51 (X2 Core) 8-Bit Internal Bus Clock and PLL Unit MP3 Decoder Unit I2S/PCM Audio Interface USB Controller MMC Interface Keyboard Interface I/O Ports IDE Interface 1 FILT X1 X2 RST ISP ALE DOUT DCLK DSEL SCLK D+ DMCLK MDAT MCMD KIN3:0 P0-P5 1 Alternate function of Port 1 3 Alternate function of Port 3 4 Alternate function of Port 4 2 AT8xC51SND1C 4109JS–8051–10/06 AT8xC51SND1C 4. Pin Description 4.1 Pinouts AT8xC51SND1C 80-pin QFP Package P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Figure 4-1. ALE ISP1/PSEN2/NC P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PVDD FILT PVSS VSS X2 X1 TST UVDD UVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AT89C51SND1C-RO (FLASH) AT83SND1C-RO (ROM) AT80C51SND1C-RO (ROMLESS) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD Notes: 1. ISP pin is only available in AT89C51SND1C product. Do not connect this pin on AT83SND1C product. 2. PSEN pin is only available in AT80C51SND1C product. D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 3 4109JS–8051–10/06 Figure 4-2. AT8xC51SND1C 81-pin BGA Package 9 P4.6 8 P2.0/ A8 7 P4.0/ MISO P4.1/ MOSI P2.1/ A9 6 P4.2/ SCK P4.3/ SS 5 VDD 4 P0.2/ AD2 P0.4/ AD4 3 P0.3/ AD3 P0.0/ AD0 P1.0/ KIN0 P1.7/ SDA 2 P5.0 ISP1/ PSEN2 NC P1.3/ KIN3 1 ALE A B C D E F G H J P4.4 P4.7 P0.1/ AD1 P1.1 P2.5/ A13 P2.4/ A12 P2.2/ A10 P2.6/ A14 P2.3/ A11 P0.6 VSS P5.1 P1.2/ KIN2 P4.5 P0.7/ AD7 P2.7/ A15 P0.5/ AD5 P1.6/ SCL P1.5 P1.4 VDD VSS FILT PVDD X1 VDD RST MCMD MCLK MDAT AVDD P3.4/ T0 P3.5/ T1 P3.3/ INT1 P3.2/ INT0 UVSS PVSS X2 DSEL SCLK DOUT P5.3 P3.7/ RD VDD TST VSS DCLK VSS AIN1 AVSS AIN0 P3.1/ TXD P3.0/ RXD D- UVDD VDD P5.2 AREFP AREFN P3.6/ WR VSS D+ Notes: 1. ISP pin is only available in AT89C51SND1C product. Do not connect this pin on AT83SND1C and AT80C51SND1C product. 2. PSEN pin is only available in AT80C51SND1C product. 4 AT8xC51SND1C 4109JS–8051–10/06 AT8xC51SND1C Figure 4-3. AT8xC51SND1C 84-pin PLCC Package NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PAVDD FILT PAVSS VSS X2 NC X1 TST UVDD UVSS 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 AT89C51SND1C-SR (FLASH) NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD 4.2 Signals All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description Signal Name Type Description Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Alternate Function P0.7:0 I/O D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 NC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 AD7:0 P1.7:0 I/O KIN3:0 SCL SDA A15:8 P2.7:0 I/O 5 4109JS–8051–10/06 Signal Name Type Description Alternate Function RXD TXD P3.7:0 I/O Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups. INT0 INT1 T0 T1 WR RD MISO MOSI SCK SS - P4.7:0 I/O Port 4 P4 is an 8-bit bidirectional I/O port with internal pull-ups. P5.3:0 I/O Port 5 P5 is a 4-bit bidirectional I/O port with internal pull-ups. Table 2. Clock Signal Description Signal Name Type Description Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected. PLL Low Pass Filter input FILT receives the RC network of the PLL low pass filter. Alternate Function X1 I - X2 O - FILT I - Table 3. Timer 0 and Timer 1 Signal Description Signal Name Type Description Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set by a low level on INT0. Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level on INT1. P3.3 P3.2 Alternate Function 6 AT8xC51SND1C 4109JS–8051–10/06 AT8xC51SND1C Signal Name Type Description Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. Alternate Function T0 I P3.4 T1 I P3.5 Table 4. Audio Interface Signal Description Signal Name DCLK DOUT DSEL Type O O O Description DAC Data Bit Clock DAC Audio Data DAC Channel Select Signal DSEL is the sample rate clock output. DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). Alternate Function - SCLK O - Table 5. USB Controller Signal Description Signal Name Type Description USB Positive Data Upstream Port This pin requires an external 1.5 KΩ pull-up to VDD for full speed operation. USB Negative Data Upstream Port Alternate Function D+ I/O - D- I/O - Table 6. MutiMediaCard Interface Signal Description Signal Name MCLK Type O Description MMC Clock output Data or command clock transfer. MMC Co