FingerChip Thermal Fingerprint Sweep Sensor

www.DataSheet4U.com Features • • • • • • • • • • • • • • • Thermal Sensitive Layer Over a 0.35 µm CMOS Array Image Zone: 0.4 x 11.6 mm Image Array: 8 × 232 = 1856 Pixels Pixel Pitch: 50 × 50 µm = 500 dpi Resolution On-chip 8-bit Analog to Digital Converter Serial Peripheral Interface (SPI) - 2 Modes: – Fast Mode at 16 Mbps Max for Imaging – Slow Mode at 200 kbps Max for Navigation and Control Die Size: 1.5 × 15 mm Operating Voltage: 2.3 to 3.6V I/O Voltage: 1.65 to 3.6V Operating Temperature Range: -40°C to 85°C Finger Sweeping Speed from 2 to 20 cm/Second Low Power: 4.5 mA (Image Acquisition), 1.5 mA (Navigation), <10 µA (Sleep Mode) Hard Protective Coating (>4 Million Sweeps) High Protection from Electrostatic Discharge Small Form Factor Packaging Description Atmel’s AT77C105A fingerprint sensor is dedicated to PDA, cellular and smartphone applications. Based on FingerChip thermal technology, the AT77C105A is a linear sensor that captures fingerprint images by sweeping the finger over the sensing area. This product embeds true hardware-based 8-way navigation and click functions as well, as enabling elimination of mechanical joystick devices. Applications • • • • • Scrolling, Menu and Item Selection for PDAs, Cellular or Smartphone Applications Cellular and Smartphones-based Security (Device Protection, Network and ISP Access, E-commerce) Personal Digital Agenda (PDA) Access User Authentication for Private and Confidential Data Access Portable Fingerprint Acquisition FingerChip® Thermal Fingerprint Sweep Sensor, Hardware Based Navigation and Click Functions, Extended I/O range (1.8-3.3V) AT77C105A Preliminary Sweep your finger to make life easier Chip-on-board Package Actual size of sensor 5419A–BIOM–01/05 Table 1. Pin Description for Chip-on-board Package: AT77C105A-CB08V Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Note: GNDD GNDA VDDD VDDA SCK TESTA MOSI VDD_IO MISO SCANEN SSS IRQ FSS RST FPL G G P P I IO I P O I I O I I I Name Type Description Not connected Not connected Not connected Not connected Digital ground supply Analog ground supply - connect to GNDD Digital power supply Analog power supply - connect to VDD Serial Port Interface (SPI) clock Reserved for the analog test, not connected Master-out slave-in data Input/output power supply - connect IO voltage compatibility accordingly Master-in slave-out data Reserved for the scan test in factory, must be grounded Slow SPI slave select (active low Interrupt line to host (active low). Digital test pin Fast SPI slave select (active low) Reset and sleep mode control (active high) Front plane, must be grounded The die attach is connected to pin 6 and must be grounded. The FPL pin must also be grounded. 2 AT77C105A [Preliminary] 5419A–BIOM–01/05 AT77C105A [Preliminary] Figure 1. Typical Application VDDD VDDD 10 kΩ IRQ MISO MOSI SCK SSS FSS SCANEN GND RST GNDA FPL GNDD VDDA TESTA VDD_IO VDDD VDD_IO 10 kΩ NC VDDD 10µF VDDA 10µF GND The pull-up must be implemented for the master controller. The noise should be lower than 30 mV peak to peak on VDDA. Figure 2. Pin Description NC NC NC NC GNDD GNDA VDDD VDDA SCK TESTA MOSI VDD_IO MISO SCANEN SSS IRQ FSS RST FPL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 The TESTA pin is only used for testing and debugging. The SCANEN pin is not used in the final application and must be connected to ground. Warning: SSS and FSS must never be low at the same time. When both SSS and FSS equal 0, the chip switches to scan test mode. With the SPI protocol, this configuration is not possible as only one slave at a time can be selected. However, this configuration works when debugging the system. 3 5419A–BIOM–01/05 Specifications Table 2. Absolute Maximum Ratings Parameter Power supply voltage Front plane Digital input Input/output pads power supply Storage temperature Lead temperature (soldering 10 seconds) Symbol VDDD, VDDA FPL SSS, FSS, SCK, MOSI VDD_IO Tstg Tleads Do not solder Comments Value -0.5 to 4.6V GND to VDD +0.5V GND to VDD +0.5V GND to VDD +0.5V -50 to +95°C Forbidden Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Recommended Conditions of Use Parameter Positive supply voltage Front plane Digital input voltage Digital output voltage Digital load Operating temperature range Maximum current on VDDA CL Tamb IVDDA Industrial “V” grade 0 Symbol VDD FPL Comments 2.5 ±5% 3.3 ±10% Must be grounded Min 2.3 Typ 2.5 3.3 GND CMOS levels CMOS levels 20 -40 to +85 60 50 Max 3.6 Unit V V V V pF °C mA Table 4. Resistance Parameter ESD On pins HBM (Human Body Model) CMOS I/O On die surface (zap gun) air discharge Mechanical Abrasion Number of cycles without lubricant Multiply by a factor of 20 for correlation with a real finger Chemical Resistance Cleaning agent, acid, grease, alcohol, diluted acetone 4 hours Internal method 200 000 MIL E 12397B 2 kV (TBC) ±16 kV (TBC) MIL-STD-883 method 3015.7 NF EN 6100-4-2 Min Value Standard Method 4 AT77C105A [Preliminary] 5419A–BIOM–01/05 AT77C105A [Preliminary] Note: TBC = To be confirmed Table 5. Explanation of Test Levels Level I II III IV V VI D Description 100% production tested at +25°C 100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample) Sample tested only Parameter is guaranteed by design and/or characterization testing Parameter is a typical value only 100% production tested at temperature extremes 100% probe tested on wafer at Tamb = +25°C Table 6. Specifications Parameter Resolution Size Yield: number of bad pixels Symbol Test Level IV IV I Min(1) Typ 50 8 × 232 5 Max(1) Unit Micron Pixel Bad pixels Power Consumption and DC Characteristics The following characteristics are applicable to the operating temperature -40°C ≤ T ≤ +85°C. Typical conditions are: power supply = 3.3V; Tamb = 25°C; FSCK = 12 MHz (1600 slices per second); duty cycle = 50% CLOAD 120 pF on digital outputs unless otherwise specified. Table 7. Power Requirements Name VDD IDD IDDNAV IDDCLI IDDSLP IDDSTB Note: Parameter Positive supply voltage Current on VDD in acquisition mode Current on VDD in navigation mode Current on VDD in click mode Current on VDD in sleep mode Current on VDD in stand-by mode 1. Min and max values are to be confirmed. Conditions Test Level I I I I I I Min(1) 2.3 3 1 0.2 Typ 2.5/3.3 4.5 1.5 0.3 Max(1) 3.6 6 2 0.5 10 UnitV mA mA mA µA Refer to “Power Management” on page 32 5 5419A–BIOM–01/05 VDD_IO = 1.8V Table 8. Digital Inputs Logic Compatibility Name IIL IIH IIOZ VIL VIH VHYST Parameter Low level input current without pullup device(1) High level input current without pull-down device(1) Tri-state output leakage without pull-up/down device(1) Low level input voltage(1) High level input voltage(1) Schmitt trigger hysteresis(1) Conditions VI = 0V VI = VDD_IO VI = 0V or VDD_IO Test Level I I IV I I IV 0.6 VDD(1) 0.15 VDD_IO 0.3 VDD_IO CMOS Min Typ Max 1 1 1 0.4 VDD_IO(1) Unit µA µA µA V V V Table 9. Digital Outputs Logic Compatibility Name VOL VOH Note: Parameter Low level output voltage High level output voltage Conditions IOL = 4 mA VDD = 1.8V ±8% IOH = -4 mA VDD = 3.3V ±10% Test Level I I 0.85 VDD CMOS Min Typ Max 0.15 VDD_IO (1) Unit V V 1. A minimum noise margin of 0.05 VDD should be taken for Schmitt trigger input threshold switching levels compared to VIL and VIH values. 6 AT77C105A [Preliminary] 5419A–BIOM–01/05 AT77C105A [Preliminary] VDD_IO = 2.3V to 3.6V Table 10. Digital Inputs Logic Compatibility Name IIL IIH IIOZ VIL VIH VHYST Parameter Low level input current without pullup device(1) High level input current without pull-down device(1) Tri-state output leakage without pull-up/down device(1) Low level input voltage(1) High level input voltage(1) Schmitt trigger hysteresis(1) Conditions VI = 0V VI = VDD_IO VI = 0V or VDD_IO Test Level I I IV I I IV 0.6 VDD_IO(1) 0.06 VDD_IO 0.09 VDD_IO CMOS Min Typ Max 1 1 1 0.5 VDD_IO(1) Unit µA µA µA V V V Table 11. Digital Outputs Logic Compatibility Name VOL Parameter Low level output voltage Conditions IOL = 4 mA VDD _IO = 2.3V to 3.6V IOH = -4 mA VDD_IO = 2.3V to 3.6V Test Level I CMOS Min Typ Max 0.10 VDD_IO (1) Unit V VOH High level output voltage I 0.90 VDD V Input/Output Voltage Level Compatibility The I/O voltage level compatibility is set by the power voltage driven on the VDD_IO pad. For 1.8V level compatibility, connect VDD_IO to a 1.8V power supply. 7 5419A–BIOM–01/05 Switching Performances The following characteristics are applicable to the operating temperature -40°C ≤ T ≤ +85°C. Typical conditions are: nominal value; Tamb = 25°C; FSCK = 12 MHz; duty cycle = 50%; CLOAD 120 pF in digital output unless specified otherwise. Table 12. Timings Parameter Clock frequency acquisition mode Clock frequency navigation mode and chip control Duty cycle (clock SCK) Reset setup time Slave select setup time Slave select hold time Note: 1. TSCK = 1/FCTRL (clock period) Symbol FACQ FCTRL DC TRSTSU TSSSU TSSHD Test Level IV I IV I I I ½ Min 8 20 TSCK(1) 50 Typ Max 16 0.2 80 Unit MHz MHz % ns ns ns ½ TSCK(1) ½ TSCK(1) Table 13. 3.3V ±10% Power Supply Parameter Data in setup time Data in hold time Data out valid Data out disable time from SS high IRQ hold time Note: All power supplies = +3.3V Symbol TSU TH TV TDIS TIRQ Test Level IV IV I IV IV 3.8 3 Min Typ 3 1 30 Max Unit ns ns ns ns µs Table 14. 2.5V ±5% Power Supply Parameter Data in setup time Data in hold time Data out valid Data out disable time from SS high IRQ hold time Note: All power supp