Thermal Fingerprint Sensor

www.DataSheet4U.com 1. Features • • • • • • • • • • • • Sensitive Layer Over a 0.35 µm CMOS Array Image Zone: 0.4 x 14 mm = 0.02" x 0.55" Image Array: 8 x 280 = 2240 pixels Pixel Pitch: 50 µm x 50 µm = 500 dpi Pixel Clock: up to 2 MHz Enabling up to 1780 Frames per Second Die Size: 1.64 x 17.46 mm Operating Voltage: 3V to 3.6V Naturally Protected Against ESD: > 16 kV Air Discharge Power Consumption: 16 mW at 3.3V, 1 MHz, 25°C Operating Temperature Range: -40°C to +85°C Chip-on-Board (COB), Chip-on-Board (COB) with Connector Complies With the European Directive for Restriction of Hazardous Substances (RoHS Directive) 2. Applications • • • • • • • • PDA (Access Control, Data Protection) Notebook, PC-add on (Access Control, e-business) PIN Code Replacement Automated Teller Machines, POS Building Access Electronic Keys (Cars, Home) Portable Fingerprint Imaging for Law Enforcement TV Access Thermal Fingerprint Sensor with 0.4 mm x 14 mm (0.02" x 0.55") Sensing Area and Digital Output (On-chip ADC) AT77C102B FingerChip® Figure 2-1. FingerChip® Packages Chip-on-board Package with Connector Chip-on-board Package (COB) Actual size Rev. 5364A–BIOM–09/05 Table 2-1. Pin Description for Chip-on-Board Package: AT77C102B-CB01YV Name GND AVE AVO TPP TPE VCC GND RST PCLK OE ACKN De0 Do0 De1 Do1 De2 Do2 De3 Do3 FPL GND Type GND Analog output Analog output Power Digital input Power GND Digital input Digital input Digital input Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output GND GND Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 The die attach is connected to pins 1, 7 and 21, and must be grounded. The FPL pin must be grounded. GND AVE AVO TPP TPE VCC GND RST PCLK OE ACKN De0 Do0 De1 Do1 De2 Do2 De3 Do3 FPL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND 21 2 AT77C102B 5364A–BIOM–09/05 AT77C102B Table 2-2. Pin Description for COB with Connector Package: AT77C102B-CB02YV(1) Name FPL Not connected Not connected DE3 DO3 DE2 DO2 DE1 DO1 DE0 DO0 AVE AVO TPP TPE VCC GND RST PCLK OE ACKN Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Analog output Analog output Power Digital input Power GND Digital input Digital input Digital input Digital output Type GND Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Note: 1. Ref. Connector: FH18-21S-0.3SHW (HIROSE). 3 5364A–BIOM–09/05 Figure 2-2. COB with Flex(1) Flex with metallizations up Flex with metallizations down Figure 2-3. Flex Output Side Flex Output (FingerChip Connector Side) Metallizations Up 3 1 2 Note: 1. Flex is not provided by Atmel. 4 AT77C102B 5364A–BIOM–09/05 AT77C102B 3. Description The AT77C102B is part of the Atmel FingerChip monolithic fingerprint sensor family for which no optics, no prism and no light source are required. The AT77C102B is a single-chip, high-performance, low-cost sensor based on temperature physical effects for fingerprint sensing. The AT77C102B has a linear shape, which captures a fingerprint image by sweeping the finger across the sensing area. After capturing several images, Atmel proprietary software can reconstruct a full 8-bit fingerprint image. The AT77C102B has a small surface combined with CMOS technology, and a Chip-on-Board package assembly. These facts contribute to a low-cost device. The device delivers a programmable number of images per second, while an integrated analogto-digital converter delivers a digital signal adapted to interfaces such as an EPP parallel port, a USB microcontroller or directly to microprocessors. No frame grabber or glue interface is therefore necessary to send the frames. These facts make AT77C102B an easy device to include in any system for identification or verification applications. Table 3-1. Parameter Positive supply voltage Temperature stabilization power Front plane Digital input voltage Storage temperature Lead temperature (soldering, 10 seconds) Absolute Maximum Ratings() Symbol VCC TPP FPL RST PCLK Tstg Tleads Do not solder Comments Value GND to 4.6 GND to 4.6 GND to VCC +0.5 GND to VCC +0.5 -50 to +95 Forbidden Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3-2. Parameter Recommended Conditions Of Use Symbol VCC FPL Must be grounded Comments Min 3V Typ 3.3V GND CMOS levels CMOS levels CL CA RA Tamb ITPP Not connected V grade 0 -40°C to +85°C 100 50 Max 3.6V Unit V V V V pF pF kΩ °C mA Positive supply voltage Front plane Digital input voltage Digital output voltage Digital load Analog load Operating temperature range Maximum current on TPP 5 5364A–BIOM–09/05 Table 3-3. Parameter ESD Resistance Min Value Standard Method On pins. HBM (Human Body Model) CMOS I/O On die surface (Zapgun) Air discharge Mechanical Abrasion Number of cycles without lubricant multiply by an estimated factor of 20 for correlation with a real finger Chemical Resistance Cleaning agent, acid, grease, alcohol, diluted acetone 2 kV ±16 kV MIL-STD-883 - method 3015.7 NF EN 6100-4-2 200 000 MIL E 12397B 4 hours Internal method Table 3-4. Specifications Explanation Of Test Levels I II III IV V VI D 100% production tested at +25°C 100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample) Sample tested only Parameter is guaranteed by design and/or characterization testing Parameter is a typical value only 100% production tested at temperature extremes 100% probe tested on wafer at Tamb = +25°C Table 3-5. Parameter Resolution Size Physical Parameter Test Level IV IV I I 20 30 Min Typ 50 8 x 280 5 47 Max Unit µm Pixel Bad pixels Ω Yield: number of bad pixels Equivalent resistance on TPP pin 6 AT77C102B 5364A–BIOM–09/05 AT77C102B . Table 3-6. 3.3V Power supply The following characteristics are applicable to the operating temperature -40°C ≤ Ta ≤ +85°C Typical conditions are: VCC = +3.3 V; Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50% Cload 120 pF on digital outputs, analog outputs disconnected unless otherwise specified Symbol Test Level Min Typ Max Unit Parameter Power Requirements Positive supply voltage Active current on VCC pin, 1 MHz Current on VCC pin, in static mode Cload = 0 pF Power dissipation on VCC Cload = 0 Current on VCC in NAP mode Analog Output Voltage range Digital Inputs Logic compatibility Logic “0” voltage Logic “1” voltage Logic “0” current Logic “1”current TPE logic “0” voltage TPE logic “1” voltage Digital Outputs Logic compatibility Logic “0” voltage Logic “1” voltage Note: (1) (1) VCC ICC PCC ICCNAP I IV I IV I 3.0 3.3 5 4 16 13 3.6 7 5 25 18 10 V mA mA mW mW µA VAVx IV 0 2.9 V CMOS VIL VIH IIL IIH IILTPE IIHTPE I I I I 1 1 0 2.3 -10 0 -10 0 0.8 VCC 0 10 0 300 V V µA µA µA µA CMOS VOL VOH I I 2.4 0.6 V V 1. With IOL = 1 mA and IOH = -1 mA 7 5364A–BIOM–09/05 . Table 3-7. Switching Performances The following characteristics are applicable to the operating temperature -40°C ≤ Ta ≤ +85°C Typical conditions are: nominal voltage; Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50% Cload 120 pF on digital and analog outputs unless otherwise specified Symbol fPCLK tHCLK tLCLK tSetup tNOOE tHRST Test Level I I I I IV IV 100 50 Min 0.5 250 250 0 Typ 1 Max 2 Unit MHz ns ns ns ns ns Parameter Clock frequency Clock pulse width (high) Clock pulse width (low) Clock setup time (high)/reset falling edge No data change Reset pulse width high Table 3-8. Parameter 3.3V ±10% Power Supply Symbol tPLHACKN tPHLACKN tPDATA tPAVIDEO tDATAZ tZDATA Test Level I I I I IV IV 34 47 Min Typ Max 145 145 120 250 Unit ns ns ns ns ns ns Output delay from PCLK to ACKN rising edge Output delay from PCLK to ACKN falling edge Output delay from PCLK to data output Dxi Output delay from PCLK to analog output AVx Output delay from OE to data high-Z Output delay from OE to data output Figure 3-1. Reset Reset RST tHRST Clock PCLK tSETUP 8 AT77C102B 5364A–BIOM–09/05 AT77C102B Figure 3-2. Read One Byte/Two Pixels fPCLK tHCLK Clock PCLK tLCLK Acknowledge ACKN tPLHACKN tPHLACKN Data output Do0-3, De0-3 Data #N-1 Data #N t PDATA Data #N+1 Video analog output AVO, AVE Data #N Data #N+1 Data #N+2 tPAVIDEO Figure 3-3. Output Enable Output enable OE Data output Do0-3, De0 -3 Hi-Z tZDATA Data output tDATAZ Hi-Z 9 5364A–BIOM–09/05 Figure 3-4. PCLK No Data Change tNOOE OE Note: OE must not change during TNOOE after the PCLK falls. This is to ensure that the output drivers of the data are not driving current, so as to reduce the noise level on the power supply. Figure 3-5. PCLK RST AT77C102B Block Diagram Clock Reset Column selection 1 dummy column 1 8 lines of 280 columns of pixels 8 2240 8 Odd Chip temperature stabilization Chip temperature sensor 4-bit ADC 4 Amp L sel ine ACKN Even 4-bit ADC 4 8 Latches De0-3 Do0-3 Analog output Output enable TPP TPE AVE AVO OE 3.1 Functional Description The circuit is divided into two main sections: sensor and data conversion. One particular column among 280 plus one is selected in the sensor array (1), then each pixel of the selected column sends its electrical information to the amplifiers (2) [one per line], then two lines at a time are selected (odd and even) so that two particular pixels send their information to the input of two 4bit analog-to-digital converters (3), so two pixels can be read for each clock pulse (4). 10 AT77C102B 5364A–BIOM–09/05 AT77C102B F