Features
• 2.7V to 3.3V Read/Write • Access Time - 90 ns • Sector Erase Architecture
– Thirty 32K Word (64K Byte) Sectors with Individual Write Lockout – Eight 4K Word (8K Byte) Sectors with Individual Write Lockout – Two 16K Word (32K Byte) Sectors with Individual Write Lockout Fast Word Program Time - 20 µs Fast Sector Erase Time - 200 ms Dual Plane Organization, Permitting Concurrent Read while Program/Erase Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors Memory Plane B: Twenty-four 32K Word Sectors Erase Suspend Capability – Supports Reading/Programming Data from Any Sector by Suspending Erase of Any Different Sector Low-power Operation – 25 mA Active – 10 µA Standby Data Polling, Toggle Bit, Ready/Busy for End of Program Detection Optional VPP Pin for Fast Programming RESET Input for Device Initialization Sector Program Unlock Command TSOP, CBGA, and µBGA Package Options Top or Bottom Boot Block Configuration Available
• • • • • • • • • • •
16-megabit (1M x 16/2M x 8) 3-volt Only Flash Memory AT49BV1604 AT49BV1604T AT49BV1614 AT49BV1614T
Description
The AT49BV16X4(T) is 2.7- to 3.3-volt 16-megabit Flash memory organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 40 sectors for erase operations. The device is offered in 48-pin TSOP and 48-ball µBGA packages. The device has CE, and OE control signals to avoid any bus (continued)
Pin Configurations
Pin Name
A0 - A19 CE OE WE RESET RDY/BUSY VPP I/O0 - I/O14 I/O15 (A-1) BYTE NC VCCQ DC
Function
Addresses Chip Enable Output Enable Write Enable Reset READY/BUSY Output Optional Power Supply for Faster Program/Erase Operations Data Inputs/Outputs I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) Selects Byte or Word Mode No Connect Output Power Supply Don’t Connect
Rev. 0925H–08/99
1
TSOP Top View Type 1
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET VPP NC A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0
µBGA Top View (Ball Down)
1 A
A13 A11 A10 A12 I/O14 A8 WE A9 I/O5 I/O6 I/O13 I/O11 I/O12 I/O4 I/O2 I/O3 VCC VPP RST A18 A19 A17 A6 I/O8 I/O9 I/O10 A7 A5 A3 CE I/O0 I/O1 A4 A2 A1 A0 GND OE
2
3
4
5
6
7
8
B
A14
AT49BV1604(T)
C
A15
D
A16
E
VCCQ I/O15
F
GND I/O7
TSOP Top View Type 1
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE RESET VPP NC RDY/BUSY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0
CBGA Top View
1 A
A3 A7 RDY/BUSY WE A17 A6 A5 I/O0 I/O8 I/O9 I/O1 NC A18 NC I/O2 I/O10 I/O11 I/O3 RESET VPP A19 I/O5 I/O12 VCC I/O4 A9 A8 A10 A11 I/O7 I/O14 I/O13 I/O6 A13 A12 A14 A15 A16 BYTE I/O15 /A-1 VSS
2
3
4
5
6
B
A4
C
A2
D
A1
E
AT49BV1614(T)
F G
A0 CE OE
H
VSS
contention. This device can be read or reprogrammed using a single 2.7V power supply, making it ideally suited for in-system programming. The device powers on in the read mode . Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector. Once the data protection for a given sector is enabled, the data in that sector cannot be changed using input levels between ground and V CC. The device is segmented into two memory planes. Reads from memory plane B may be performed even while
program or erase functions are being executed in memory plane A and vice versa. This operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend feature. This feature will put the Erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the same memory plane. There is no reason to suspend the erase operation if the data to be read is in the other memory plane. The end of a program or an Erase cycle is detected by the Ready/Busy pin, Data polling, or by the toggle bit.
2
AT49BV1604(T)/1614(T)
AT49BV1604(T)/1614(T)
A V PP pin is provided to improve program/erase times. This pin can be tied to V CC. To take advantage of faster programming and erasing, the pin should supply 4.5 to 5.5 volts during program and erase operations. A six byte command (bypass unlock) sequence to remove th e req uirement of ente ring the three byte prog ra m sequence is offered to further improve programming time. After entering the six byte code, only single pulses on the write control lines are required for writing into the device. This mode (single pulse byte/word program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 50 ns and then bringing it back to VCC. Erase and Erase Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six byte code reside in the software of the final product but only exist in external programming code. For the AT49BV1614(T), the BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic “1”, the device is in word configuration, I/O0-I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-stated, and the I/O15 pin is used as an input for the LSB (A-1) address function.
Block Diagram
I/O0 - I/O15/A-1
OUTPUT BUFFER
INPUT BUFFER
OUTPUT MULTIPLEXER
A0 - A19
INPUT BUFFER
DATA REGISTER
IDENTIFIER REGISTER
STATUS REGISTER
COMMAND REGISTER
ADDRESS LATCH DATA COMPARATOR
CE WE OE RESET BYTE
RDY/BUSY WRITE STATE MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE VOLTAGE SWITCH
VPP
VCC GND X-DECODER
PLANE B SECTORS
PLANE A SECTORS
Device Operation
READ: The AT49BV16X4(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line contro l gives design ers flexib ility in preventing bu s contention. COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are don't care inputs for the command codes).
3
The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the Read or Standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RESET pin any sector can be reprogrammed even if the sector lockout feature has been enabled (see Sector Programming Lockout Override section). ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase commands. CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC. If the sector lockout has been enabled, the Chip Erase will not erase the data in the sector that has been locked; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into forty sectors (SA0 - SA39) that can be individually erased. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a section is tSEC. When the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command). Once a sector has been protected, data in the protected sectors cannot be changed unless the RESET pin is taken to 12V ± 0.5V. An attempt to erase a sector that has been protected will result in the operation terminating in 2 µs. BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical “0
