8-megabit 2.7-volt Only Serial DataFlash

Features • • • • • • • • • • • • • • 100% Compatible to AT45DB081 Single 2.7V - 3.6V Supply Serial Interface Architecture Page Program Operation – Single Cycle Reprogram (Erase and Program) – 4096 Pages (264 Bytes/Page) Main Memory Optional Page and Block Erase Operations Two 264-byte SRAM Data Buffers – Allows Receiving of Data while Reprogramming of Nonvolatile Memory Continuous Read Capability through Entire Array Internal Program and Control Timer Low Power Dissipation – 4 mA Active Read Current Typical – 2 µA CMOS Standby Current Typical 13 MHz Max Clock Frequency Hardware Data Protection Feature Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3 CMOS and TTL Compatible Inputs and Outputs Commercial and Industrial Temperature Ranges 8-megabit 2.7-volt Only Serial DataFlash® AT45DB081A Recommend using AT45DB081B for new designs. Description The AT45DB081A is a 2.7-volt only, serial interface Flash memory suitable for in-system reprogramming. Its 8,650,752 bits of memory are organized as 4096 pages of 264 bytes each. In addition to the main memory, the AT45DB081A also contains two SRAM data buffers of 264 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed. Unlike conventional Flash www.DataSheet4U.com (continued) Pin Configurations Pin Name CS SCK SI SO WP RESET RDY/BUSY Function Chip Select Serial Clock Serial Input Serial Output Hardware Page Write Protect Pin Chip Reset Ready/Busy PLCC CS NC NC GND VCC NC NC GND NC NC CS SCK SI SO NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RDY/BUSY RESET WP NC NC VCC GND NC NC NC CS SCK SI SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC TSOP Top View Type 1 SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC NC NC WP RESET RDY/BUSY NC NC NC NC NC NC NC NC CBGA Top View through Package 1 A NC NC NC VCC 2 3 14 15 16 17 18 19 20 SCK SI SO NC NC NC NC NC NC 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 WP RESET RDY/BUSY NC NC NC NC NC NC B NC NC GND C SCK D CS RDY/BSY WP E SO SI NC NC RESET NC NC F NC NC NC DC DC NC NC NC G NC Rev. 1634D–01/01 Note: PLCC package pins 16 and 17 are DON’T CONNECT. 1 memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a serial interface to sequentially access its data. The simple serial interface facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. Typical applications for the DataFlash are digital voice storage, image storage, and data storage. The device operates at clock frequencies up to 13 MHz with a typical active read current consumption of 4 mA. To allow for simple in-system reprogrammability, the AT45DB081A does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB081A is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming cycles are self-timed, and no separate erase cycle is required before programming. Block Diagram WP FLASH MEMORY ARRAY PAGE (264 BYTES) BUFFER 1 (264 BYTES) BUFFER 2 (264 BYTES) SCK CS RESET VCC GND RDY/BUSY I/O INTERFACE SI SO Memory Array To provide optimal flexibility, the memory array of the AT45DB081A is divided into three levels of granularity comprising of sectors, blocks and pages. The Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a pageby-page basis; however, the optional erase operations can be performed at the block or page level. 2 AT45DB081A AT45DB081A Memory Architecture Diagram SECTOR ARCHITECTURE SECTOR 0 = 8 Pages 2112 bytes (2K + 64) SECTOR 1 = 248 Pages 65,472 bytes (62K + 1984) BLOCK ARCHITECTURE SECTOR 0 BLOCK 0 BLOCK 1 PAGE ARCHITECTURE 8 Pages PAGE 0 PAGE 1 SECTOR 1 BLOCK 2 BLOCK 0 SECTOR 2 = 256 Pages 67,584 bytes (64K + 2K) PAGE 6 PAGE 7 PAGE 8 BLOCK 30 BLOCK 31 SECTOR 3 = 512 Pages 135,168 bytes (128K + 4K) SECTOR 4 = 512 Pages 135,168 bytes (128K + 4K) SECTOR 2 BLOCK 33 BLOCK 1 BLOCK 32 PAGE 9 PAGE 14 PAGE 15 BLOCK 62 BLOCK 63 BLOCK 64 SECTOR 8 = 512 Pages 135,168 bytes (128K + 4K) BLOCK 65 PAGE 16 PAGE 17 PAGE 18 SECTOR 9 = 512 Pages 135,168 bytes (128K + 4K) PAGE 4093 BLOCK 510 BLOCK 511 PAGE 4094 PAGE 4095 Block = 2112 bytes (2K + 64) Page = 264 bytes (256 + 8) Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses and data are transferred with the most-significant bit (MSB) first. Buffer addressing is referenced in the datasheet using the terminology BFA8-BFA0 to denote the nine address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA11-PA0 and BA8-BA0 where PA11-PA0 denotes the 12 address bits required to designate a page address and BA8-BA0 denotes the nine address bits required to designate a byte address within the page. Mode 3. A separate opcode (refer to Table 1 on page 8 for a complete list) is used to select which category will be used for reading. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle sequences for each mode. CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked into the device followed by 24 address bits and 32 don’t care bits. The first three bits of the 24-bit address sequence are reserved for upward and downward compatibility to larger and smaller density devices (see Notes under “Command Sequence for Read/Write Operations” diagram). The next 12 address bits (PA11-PA0) specify which page of the main memory array to read, and the last nine bits (BA8-BA0) of the 24-bit address sequence specify the starting byte address within the page. The 32 don’t care bits that follow the 24 address bits are needed to initialize the read operation. Following the 32 don’t care bits, additional clock pulses on the SCK pin will result in serial data being output on the SO (serial output) pin. Read Commands By specifying the appropriate opcode, data can be read from the main memory or from either one of the two data buffers. The DataFlash supports two categories of read modes in relation to the SCK signal. The differences between the modes are in respect to the inactive state of the SCK signal as well as which clock cycle data will begin to be output. The two categories, which are comprised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI 3 The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits and the reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. The maximum SCK frequency allowable for the Continuous Array Read is defined by the f CAR specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. BURST ARRAY READ: The Burst Array Read operation functions almost identically to the Continuous Array Read operation but allows much higher read throughputs by utilizing faster clock frequencies. The Burst Array Read command allows the device to burst an entire page of data out at the maximum SCK frequency defined by the fBAR parameter. Differences between the Burst Array Read and Continuous Array Read operations are limited to timing only. The opcodes utilized and the opcode and addressing sequence for the Burst Array Read are identical to the Continuous Array Read. The opcode of 68H or E8H must be clocked into the device followed by the 24 address bits and 32 don’t care bits. Following the 32 don’t care bits, additional clock pulses on the SCK pin will result in serial data being output on the SO (serial output) pin. As with the Continuous Array Read, the CS pin must remain low during the loading of the opcode, the address bits, the don�