• High Performance, Low Power AVR®32 32-Bit Microcontroller
– 210 DMIPS throughput at 150 MHz
– 16 KB instruction cache and 16 KB data caches
– Memory Management Unit enabling use of operating systems
– Single-cycle RISC instruction set including SIMD and DSP instructions
– Java Hardware Acceleration
• Multimedia Co-Processor
– Vector Multiplication Unit for video acceleration through color-space conversion
(YUV<->RGB), image scaling and filtering, quarter pixel motion compensation
• Multi-hierarchy bus system
– High-performance data transfers on separate buses for increased performance
• Data Memories
– 32KBytes SRAM
• External Memory Interface
– SDRAM, DataFlash™, SRAM, Multi Media Card (MMC), Secure Digital (SD),
– Compact Flash, Smart Media, NAND Flash
• Direct Memory Access Controller
– External Memory access without CPU intervention
• Interrupt Controller
– Individually maskable Interrupts
– Each interrupt request has a programmable priority and autovector address
• System Functions
– Power and Clock Manager
– Crystal Oscillator with Phase-Lock-Loop (PLL)
– Watchdog Timer
– Real-time Clock
• 6 Multifunction timer/counters
– Three external clock inputs, I/O pins, PWM, capture and various counting
• 4 Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– 115.2 kbps IrDA Modulation and Demodulation
– Hardware and software handshaking
• 3 Synchronous Serial Protocol controllers
– Supports I2S, SPI and generic frame-based protocols
• Two-Wire Interface
– Sequential Read/Write Operations, Philips’ I2C© compatible
• Liquid Crystal Display (LCD) interface
– Supports TFT displays
– Configurable pixel resolution supporting QCIF/QVGA/VGA/SVGA configurations.
• Image Sensor Interface
– 12-bit Data Interface for CMOS cameras
• Universal Serial Bus (USB) 2.0 High Speed (480 Mbps) Device
– On-chip Transceivers with physical interface
• 2 Ethernet MAC 10/100 Mbps interfaces
– 802.3 Ethernet Media Access Controller
– Supports Media Independent Interface (MII) and Reduced MII (RMII)
• 16-bit stereo audio DAC
– Sample rates up to 50 kHz
• On-Chip Debug System
– Nexus Class 3
– Full speed, non-intrusive data and program trace
– Runtime control and JTAG interface
– AT32AP7000: 256-ball CTBGA 1.0mm pitch/160 GPIO pins
• Power supplies
– 1.65V to1.95V VDDCORE
– 3.0V to 3.6V VDDIO
1. Part Description
The AT32AP7000 is a complete System-on-chip application processor with an AVR32 RISC
processor achieving 210 DMIPS running at 150 MHz. AVR32 is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular empha-
sis on low power consumption, high code density and high application performance.
AT32AP7000 implements a Memory Management Unit (MMU) and a flexible interrupt controller
supporting modern operating systems and real-time operating systems. The processor also
includes a rich set of DSP and SIMD instructions, specially designed for multimedia and telecom
AT32AP7000 incorporates SRAM memories on-chip for fast and secure access. For applica-
tions requiring additional memory, external 16-bit SRAM is accessible. Additionally, an SDRAM
controller provides off-chip volatile memory access as well as controllers for all industry standard
off-chip non-volatile memories, like Compact Flash, Multi Media Card (MMC), Secure Digital
(SD)-card, SmartCard, NAND Flash and Atmel DataFlash™.
The Direct Memory Access controller for all the serial peripherals enables data transfer between
memories without processor intervention. This reduces the processor overhead when transfer-
ring continuous and large data streams between modules in the MCU.
The Timer/Counters includes three identical 16-bit timer/counter channels. Each channel can be
independently programmed to perform a wide range of functions including frequency measure-
ment, event counting, interval measurement, pulse generation, delay timing and pulse width
AT32AP7000 also features an onboard LCD Controller, supporting single and double scan
monochrome and color passive STN LCD modules and single scan active TFT LCD modules.
On monochrome STN displays, up to 16 gray shades are supported using a time-based dither-
ing algorithm and Frame Rate Control (FRC) method. This method is also used in color STN
displays to generate up to 4096 colors.
The LCD Controller is programmable for supporting resolutions up to 2048 x 2048 with a pixel
depth from 1 to 24 bits per pixel.
A pixel co-processor provides color space conversions for images and video, in addition to a
wide variety of hardware filter support
The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC modules
provides on-chip solutions for network-connected devices.
Synchronous Serial Controllers provide easy access to serial communication protocols, audio
standards like I2S and frame-based protocols.
The Java hardware acceleration implementation in AVR32 allows for a very high-speed Java
byte-code execution. AVR32 implements Java instructions in hardware, reusing the existing
RISC data path, which allows for a near-zero hardware overhead and cost with a very high
The Image Sensor Interface supports cameras with up to 12-bit data buses.
PS2 connectivity is provided for standard input devices like mice and keyboards.
AT32AP7000 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive
real-time trace, full-speed read/write memory access in addition to basic runtime control.
The C-compiler is closely linked to the architecture and is able to utilize code optimization fea-
tures, both for size and speed.
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