512K x 8 SRAM

SRAM Austin Semiconductor, Inc. 512K x 8 SRAM Ultra Low Power SRAM AVAILABLE AS MILITARY SPECIFICATION • SMD 5962-956131,2 • MIL STD-8831 AS5C4009 PIN ASSIGNMENT (Top View) 32-Pin DIP, 32-Pin SOJ & 32-Pin TSOP FEATURES • Ultra Low Power with 2V Data Retention (0.2mW MAX worst case Power-down standby) • Fully Static, No Clocks • Single +5V ±10% power supply • Easy memory expansion with CE and OE options • All inputs and outputs are TTL-compatible • Three state outputs • Operating temperature range: Ceramic -55oC to +125oC & -40oC to +85oC Plastic -40oC to +85oC3 1. Not applicable to plastic package 2. Applies to CW package only. 3. Contact factory for -55oC to +125oC www.DataSheet4U.com A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 A17 WE A13 A8 A9 A11 OE A10 CE I/08 I/07 I/06 I/05 I/04 OPTIONS MARKING • Timing 55ns access -55 4 70ns access -70 85ns access -85 100ns access -100 • Packages Ceramic Dip (600 mil) CW Ceramic SOJ5 ECJ Plastic TSOP DG • Options 2V data retention/very low power L I/01 I/02 I/03 Vss No. 112 No. 502 No. 1002 GENERAL DESCRIPTION The AS5C4009 is organized as 524,288 x 8 SRAM utilizing a special ultra low power design process. ASI’s pinout adheres to the JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32 pin version allows for easy upgrades from the 1 meg SRAM design. For flexibility in memory applications, ASI offers chip enable (CE) and output enable (OE) capabilities. These features can place the outputs in High-Z for additional flexibility in system design. This devices operates from a single +5V power supply and all inputs and outputs are fully TTL-compatible. Writing to these devices is accomplished when write enable (WE) and CE inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE go LOW. The device offers a reduced power standby mode when disabled, by lowering VCC to 2V and maintaining CE = 2V. This allows system designers to meet ultra low standby power requirements. 4. For DG package, contact factory 5. Contact Factory NOTE: Not all combinations of operating temperature, speed, data retention and low power are necessarily available. Please contact the factory for availability of specific part number combinations. Pin Name Function WE Write Enable Input CE Chip Select Input OE Output Enable Input A0 - A18 Address Inputs I/O1 - I/O8 Data Inputs/Outputs Vcc Power Vss Ground For more products and information please visit our web site at www.austinsemiconductor.com AS5C4009 Rev. 5.0 6/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM Clk. gen. Precharge circuit AS5C4009 A18 A16 A14 A12 A7 A6 A5 A4 A1 A0 Row select Memory Array 1024 rows 512 x 8 columns I/O1 I/O8 Data cont I/O Circuit Column Select Data cont A9 A8 A13 A17 A15 A10 A11 A3 A2 CE WE OE Control logic AS5C4009 Rev. 5.0 6/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss...................-.5V to +7.0V Voltage on any pin Relative to Vss..........................-.5V to +7.0V Storage Temperature ....................................-65°C to +150°C Operating Temperature Range.............................-55oC to +125oC Soldering Temperature Range...............................................260oC Maximum Junction Temperature**....................................+150°C Power Dissipation...................................................................1.0W AS5C4009 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < 125oC; Vcc = 5V +10%) PARAMETER/CONDITION Input Leakage Current (VIN = VSS to VCC) Output Leakage Current (CE=VIH or OE=VIH or WE=VIL, VIO=VSS to VCC) Output Low Voltage (IOL = 2.1mA) Output High Voltage (IOH = -1.0 mA) Supply Voltage Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL ILI ILO VOL VOH VCC VIH VIL MIN -5 -5 -2.4 4.5 2.2 -0.5 MAX 5 5 0.4 -5.5 Vcc +0.5 0.8 UNITS µΑ µΑ V V V V V 15 15 15 1, 15 2, 15 NOTES PARAMETER Power Supply Current: Operating CONDITIONS Cycle Time = Min., 100% Duty Cycle, IIO = 0mA, CE = VIL, VIN = VIH or VIL TTL CE = VIH, Other inputs = VIL or VIH CE = Vcc -0.2V, Other inputs = 0 ~ Vcc SYM Icc1 -55 100 MAX -70 -85 90 80 -100 UNITS NOTES 70 mA 3 ISB 6 6 6 6 mA Power Supply Current: Standby CMOS ISB1 0.75 0.75 0.75 0.75 mA AS5C4009 Rev. 5.0 6/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SRAM Austin Semiconductor, Inc. CAPACITANCE PARAMETER Input Capacitance Input/Output Capactiance CONDITIONS o TA = 25 C, f = 1MHz VCC = 5V AS5C4009 SYMBOL VIN=0V VIO=0V CIN CIO MAXIMUM 8 10 UNITS pF pF NOTES 4 4 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55oC < TA < 125oC; Vcc = 5V +10%) DESCRIPTION READ Cycle READ cycle Time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Chip Enable to power-up time Chip disable to power-down time Output Enable access time Output Enable to output in Low-Z Output disable to output in High-Z WRITE Cycle WRITE cycle time Chip Enable to end of write Address valid to end of write Address setup time Address hold from end of write WRITE pulse width Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z SYM t RC t AA t ACE t OH t LZCE t HZCE t PU t PD t AOE t LZOE t HZOE t WC t CW t AW t AS t AH t WP1 t DS t DH t LZWE t HZWE -55 MIN MAX 55 55 55 10 10 20 0 55 30 5 20 55 50 50 0 0 50 30 0 5 25 -70 MIN MAX 70 70 70 10 10 25 0 70 35 5 25 70 60 60 0 0 60 30 0 5 25 -85 MIN MAX 85 85 85 10 10 30 0 85 40 5 30 85 70 70 0 0 70 35 0 5 30 -100 MIN MAX UNITS NOTES 100 100 100 10 10 30 0 100 45 5 30 100 80 80 0 0 80 40 0 5 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4,6 4,6 4,6 4,6 4,6 4,6 4 4 AS5C4009 Rev. 5.0 6/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM Austin Semiconductor, Inc. AS5C4009 AC TEST CONDITIONS Input pulse levels ................................... Vss to 3.0V Input rise and fall times ....................................... 3ns Input timing reference levels ............................. 1.5V Output reference levels ..................................... 1.5V Output load ......................................... See Figures 1 Q 50167 ohms ohms 1.73V C C=30pF = 100pF Fig. 1 Output Load Equivalent NOTES 1. 2. 3. 4. 5. 6. Overshoot: Vcc +3.0V for pulse width < 20ms. Undershoot: -3V for pulse width < 20ms. ICC is dependent on output loading and cycle rates. This parameter is guaranteed but not tested. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE. WE is HIGH for READ cycle. Device is continuously selected. Chip enables and output enables are held in their active state. Address valid prior to, or coincident with, latest occurring chip enable. 10. tRC = Read Cycle Time. 11. Chip enable and write enable can initiate and terminate a WRITE cycle. 12. Output enable (OE) is inactive (HIGH). 13. Output enable (OE) is active (LOW). 14. ASI does not warrant functionality nor reliability of any product in which the junction temperature exceeds 150°C. Care should be taken to limit power to acceptable levels. 15. All voltage referenced to Vss (GND). 7. 8. 9. DATA RETENTION ELECTRICAL CHARACTERISTICS DESCRIPTION VCC for Retention Data Data Retention Current VIN > (VCC - 0.2V) Chip Deselect to Data Retention Time Operation Recovery Time VCC = 3V ICCDR tCDR tR 0 5 200 CONDITIONS CE > (VCC - 0.2V) VCC = 2V SYMBOL VDR ICCDR MIN 2 MAX 100 UNITS V µA µA ns ms 4 4, 10 NOTES AS5C4009 Rev. 5.0 6/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 54321 54321 54321 54321 54 3 11 543221 54321 54321 54321 5432 109876543210987654326 09876543210987654321154321 987 109876543210987654316 00987654321098765431154321 987 19876543210987654322154321 09876543210987654321154321 9826 10987654321098765437 098765432109876543226 987 1 00 65 19876543210987654322321 09876543210987654321121 09876543210987654323 987654321098765434 654 19876543210987654321121 09876543210987654321121 654 4 109876543210987654313 009876543210987654321 6523 tOH t OE t HZ 3210987652109876543210987654321 4309876543210987654321 21 3210987652109876543210987654321 4321 21 3210987652109876543210987654321 4309876543210987654321 3210987652109876543210987654321 4309876543210987654321 21 654309876543210987654321 430987654321098765432 21 652109876543210987654321 2109876543210987654321 21 652109876543210987654321 4321 1 652109876543210987654321 4321 7654220987654321 3 765 76542119876543214321 311 20 7654321 76542119876543214321 320 765 76542119876543214321 320 765 76542119876543214321 320 765 65 76542119876543214321 320 1 721 DATA OUT ADDRESS CE Controlled VCC 4.5V ADDRESS OE CE CE GND 2.2V VDR Austin Semiconductor, Inc. Previous Data Valid READ CYCLE NO. 1 1 (Address Controlled, CE = OE = VIL, WE = VIH