128K x 8 SRAM RUGGEDIZED PLASTIC HIGH SPEED SRAM

SRAM Austin Semiconductor, Inc. 128K x 8 SRAM RUGGEDIZED PLASTIC HIGH SPEED SRAM FEATURES • • • • • • • • Access times of 15, 20 and 25 ns Fast output enable (t ) for cache applications AOE Low active power Low standby power Fully static operation, no clock or refresh required TTL Compatible Inputs and Outputs Single +5V power supply Package in Industry-standard 32-pin SOJ NC A6 A5 A4 A3 A2 A1 A0 A16 A15 A14 A13 I/O0 I/O1 I/02 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A7 CE2 WE A8 A9 A10 A11 OE A12 CE 1 I/O7 I/O6 I/O5 I/O4 I/O3 AS5C1008 PIN ASSIGNMENT (Top View) 32-Pin Plastic SOJ (DJ) OPTIONS • Timing 15ns access 20ns access www.DataSheet4U.com 25ns access • Package Plastic SOJ* MARKING -15 -20 -25 DJ No. 905 • Operating Temperature Ranges -Military (-55oC to +125oC) -Industrial (-40oC to +85oC) XT IT PIN FUNCTIONS A0 - A16 WE Address Inputs Write Enable Chip Enable Output Enable Data Inputs/Outputs Power Ground No Connection GENERAL DESCRIPTION The ASI AS5C1008 is a high speed, low power, 128K by 8-bit ruggedized plastic (COTS) CMOS Static RAM. It is fabricated using high performance, CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 15ns (Max) over the military and industrial temperature ranges. When Chip Enable (CE) is HIGH, the device assumes a standby mode at which the power dissipation can be reduced down to 125mW (max) at CMOS input levels. Easy memory expansion is provided by using asserted LOW CE and asserted HIGH CE2, and asserted LOW write enable (WE) controls both writing and reading of the memory. TheAS5C1008 is pin-compatible with other 128K x 8 SRAM's in the SOJ package. CE1, CE2 OE I/O0 - I/O7 VCC VSS NC For more products and information please visit our web site at www.austinsemiconductor.com *For ceramic versions of this product, please see the MT5C1008 datasheet. AS5C1008 Rev. 3.5 1/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Vcc Supply Relative to GND...................................-0.5V to +7.0V Voltage on any pin Relative to GND.........-0.5V to Vcc +7.0V Storage Temperature ............................................-65°C to +150°C Ambient Temperature with Power Applied........-55oC to +125oC Short Circuit Output Current.................................................260oC Power Dissipation...................................................................1.0W AS5C1008 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL BLOCK DIAGRAM A0 Address A16 Decoder Memory Matrix I/O0 Data I/O7 Input Data Control Column I/O CE1 CE2 WE OE AS5C1008 Rev. 3.5 1/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM Austin Semiconductor, Inc. AS5C1008 ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC VIH and CE2 > VIL, f = fmax -15 -20 -25 SYMBOL MIN MAX MIN MAX MIN MAX UNITS ICC1 ISB1 180 150 140 mA 90 75 70 mA Vcc=MAX, CE1 > Vcc -0.2V, or CE2 CMOS Standby Current < 0.2V, VIN > Vcc -0.2V and CMOS Inputs VIN < 0.2V, f = 0 Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage GND < VIN < Vcc GND < VOUT < Vcc Output Disabled Vcc = MIN, IOH = -4.0 mA Vcc = MIN, IOL = 8.0 mA ISB2 ILI ILO VOH VOL VIH VIL 2.2 -0.5 -10 -10 2.4 10 10 10 mA µA µA V 10 10 -10 -10 2.4 10 10 -10 -10 2.4 10 10 0.4 Vcc +0.5 0.8 0.4 Vcc 2.2 +0.5 -0.5 0.8 2.2 -0.5 0.4 Vcc +0.5 0.8 V V V PIN DESCRIPTIONS A0 - A16: Address Inputs These 17 address inputs select one of the 131,072 8-bit words in the RAM. CE1: Chip Enable 1 Input CE1 is asserted LOW to read from or write to the device. If Chip Enable 1 is deasserted, the device is deselected and is in standby power mode. The I/O pins will be in the high-impedance state when the device is deselected. CE2: Chip Enable 2 Input CE2 is asserted HIGH to read from or write to the device. If Chip Enable 2 is deasserted, the device is deselected and is in standby power mode. The I/O pins will be in the high-impedance state when the device is deselected. OE: Output Enable Input The Output Enable Input is asserted LOW. If asserted LOW while CE1 is asserted (LOW) and CE2 is asserted (HIGH) and WE is deasserted (HIGH), data from the SRAM will be present on the I/O pins. The I/O pins will be in the high-impedance state when OE is deasserted. WE: Write Enable Input The Write Enable input is asserted LOW and controls read and write operations. When CE1 and WE are both asserted (LOW) and CE2 is asserted (HIGH) input data present on the I/O pins will be written into the selected memory location. AS5C1008 Rev. 3.5 1/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SRAM Austin Semiconductor, Inc. AS5C1008 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55oC VIH) Data Set-up Time Data Hold Time Write Disable to Output in Low-Z Write Enable to Output in High-Z SYMBOL tRC tAA tACE tOH tLZCE tHZCE tAOE tLZOE tHZOE tWC tCW tAW tAS tAH tWP tDS tDH tLZWE tHZWE 15 12 12 0 0 12 8 0 5 7 0 7 20 15 15 0 0 15 10 0 5 9 3 3 7 7 0 8 25 20 20 0 0 20 15 0 5 10 1 -20 MIN 20 15 15 3 3 8 7 0 20 20 3 3 MAX MIN 25 -25 MAX UNIT ns 25 25 ns ns ns ns 10 10 ns ns ns 10 ns ns ns ns ns ns ns ns ns ns ns MIN 15 MAX NOTE: 1. tLZCE, tLZWE, tHZCE, tLZOE, and tHZOEare simulated values. AS5C1008 Rev. 3.5 1/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM Austin Semiconductor, Inc. CAPACITANCE (TA = +25oC, f = 1.0 MHz) PARAMETER Input Capacitance Output Capacitance CONDITION VIN = 0V VOUT = 0V SYMBOL CIN COUT MAX 6 8 UNIT pF pF AS5C1008 AC TEST CONDITIONS Input Pulse Levels.......................................................GND to 3.0V Input Rise and Fall Times..........................................................3ns Input Timing Reference Levels................................................1.5V Output Reference Levels..........................................................1.5V Output Load..................................................................See Figure 1 +5V 480Ω Q 255Ω 30 pF Q 255Ω +5V 480Ω 5 pF for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, and tHZOE Fig. 1 OUTPUT LOAD EQUIVALENT AS5C1008 Rev. 3.5 1/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 098765432109876543216 109876543210987654326 987 10987654321098765431154321 09876543210987654322154321 987 10987654321098765432154321 09876543210987654321154321 987 109876543210987654326 098765432109876543216 987 098765432109876543216 109876543210987654326 987 109876543210987654316 09876543210987654322154321 987 10987654321098765432154321 09876543210987654321154321 987 109876543210987654326 09876543210987654321154321 987 t AH 8765432176543210987654321 439876543210987654321 021 8765109876543210987654321 109876543210987654321 098 8765109876543210987654321 1098 4321 8765432176543210987654321 87654321 098 8765109876543210987654321 1098 432176543210987654321 8765432176543210987654321 109876543210987654321 8765432176543210987654321 109876543210987654321 098 tAW ADDR WRITE CYCLE TIMING (WE CONTROLLED, OE = LOW) ADDR DOUT DOUT CE1 CE1 OE CE2 CE2 NOTES: 1. CE is HIGH for READ cycle. 2. At any given temperature and voltage condition, tHZCE is less than tLZCE. NOTE: 1. CE is HIGH for READ cycle. Austin Semiconductor, Inc. High-Z PREVIOUS DATA VALID READ CYCLE TIMING 2 (1) READ CYCLE TIMING 1(1) tLZOE tLZCE tAS 54321 54321 54321 54321 DOUT 4321 4321 4321 4321 AS5C1008 Rev. 3.5 1/01 WE DIN t OH tACE t AOE 6 tHZWE t AA tRC tWC tRC tCW t WP2 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. DATA VALID tDS DATA VALID High-Z DATA VALID tHZCE tLZWE t DH tHZCE(2) UNDEFINED DON’T CARE AS5C1008 SRAM 4321 4321 4321 4321 098765432109876543215 10987654321098765432 876 109876543210987654315 0987654321098765432214321 876 1098765432109876543214321 0987654321098765432114321 876 109876543210987654325 0987654321098765432114321 8765 876 0987654321098765432154321 109876543210987654325 876 109876543210987654315 0987654321098765432214321 109876543210987654321 0987654321098765432114321 876 871 1098765432109876543214321 0987654321098765432114321 109876543210987654365 098765432109876543225 876 t AH 8765409876543210987654321 39876543210987654321 21 8765409876543210987654321 39876543210987654321 21 8765409876543210987654321 321 8765409876543210987654321 321 87654321 1 8765409876543210987654321 32876543210987654321 09876543210987654321 9 8765409876543210987654321 39876543210987654321 21 8765409876543210987654321 3287654321098765432