4 Meg x 16 SDRAM Synchronous DRAM Memory

SDRAM Austin Semiconductor, Inc. 4 Meg x 16 SDRAM Synchronous DRAM Memory FEATURES • • • • • • • • • • • • • www.DataSheet4U.com AS4SD4M16 PIN ASSIGNMENT (Top View) 54-Pin TSOP Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8 or full page Auto Precharge and Auto Refresh Modes Self Refresh Mode (Industrial, -40°C to 85° C only) 4,096-cycle refresh LVTTL-compatible inputs and outputs Single +3.3V ±0.3V power supply Longer lead TSOP for improved reliability (OCPL*) Short Flow / Long Flow Test Screening Options OPTIONS • • MARKING 4M16 No. 901 Note: “” indicates an active low. Configurations 4 Meg x 16 (1 Meg x 16 x 4 banks) Plastic Package - OCPL* 54-pin TSOP (400 mil) DG Timing (Cycle Time) 8ns; tAC = 6.5ns @ CL = 3 ( tRP - 24ns) 10ns; tAC = 9ns @ CL = 2 Operating Temperature Ranges -Military (-55°C to +125° C) -Industrial Temp (-40°C to 85° C) • -8 -10 • XT IT 4 Meg x 16 Configuration 1 Meg x 16 x 4 banks Refresh Count 4K Row Addressing 4K (A0-A11) Bank Addressing 4 (BA0, BA1) Column Addressing 256 (A0-A7) KEY TIMING PARAMETERS SPEED GRADE -8 -10 -8 -10 CLOCK ACCESS TIME FREQUENCY CL = 2** CL = 3** 125 MHz – 6.5ns 100 MHz – 7ns 83 MHz 9ns – 66 MHz 9ns – SETUP TIME 2ns 3ns 2ns 3ns HOLD TIME 1ns 1ns 1ns 1ns *Off-center parting line **CL = CAS (READ) latency For more products and information please visit our web site at www.austinsemiconductor.com AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SDRAM Austin Semiconductor, Inc. GENERAL DESCRIPTION The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 6,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randomaccess operation. The 64Mb SDRAM is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. AS4SD4M16 AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SDRAM Austin Semiconductor, Inc. TABLE OF CONTENTS Functional Block Diagram - 4 Meg x 16 ........................................ 4 Pin Descriptions ............................................................................. 5 Functional Description ................................................................. 6 Initialization ............................................................................. 6 Register Definition ................................................................. 6 Mode Register ................................................................ 6 Burst Length ................................................................... 6 Burst Type ....................................................................... 7 CAS Latency ................................................................... 8 Operating Mode ............................................................. 8 Write Burst Mode .......................................................... 8 Commands ....................................................................................... 9 Truth Table 1 (Commands and DQM Operation) ......................... 9 Command Inhibit .................................................................... 10 No Operation (NOP) .................................................................10 Load Mode Register ............................................................. 10 Active ....................................................................................... 10 Read .......................................................................................... 10 Write ......................................................................................... 10 Precharge ................................................................................. 10 Auto Precharge ...................................................................... 10 Burst Terminate ...................................................................... 11 Auto Refresh .......................................................................... 11 Self Refresh ............................................................................. 11 Operation ..................................................................................... 12 Bank/Row Activation ............................................................ 12 Reads ........................................................................................ 13 Writes ....................................................................................... 19 Precharge................................................................................... 21 Power-Down...............................................................................21 Clock Suspend......................................................................... 22 Burst Read/Single Write ...........................................................22 Concurrent Auto Precharge ................................................. 23 Truth Table 2 (CKE) ......................................................................25 Truth Table 3 (Current State, Same Bank) ................................. 26 Truth Table 4 (Current State, Different Bank) ........................... 28 Absolute Maximum Ratings ........................................................ 30 DC Electrical Characteristics and Operating Conditions......... 30 ICC Specifications and Conditions .............................................. 30 Capacitance ..................................................................................... 31 AC Electrical Characteristics (Timing Table) ............................31 Timing Waveforms Initialize and Load Mode Register ..................................... 34 Power-Down Mode ................................................................ 35 Clock Suspend Mode ........................................................... 36 Auto Refresh Mode .............................................................. 37 Self Refresh Mode ................................................................. 38 Reads Read - Without Auto Precharge ................................. 39 Read - With Auto Precharge ....................................... 40 Alternating Bank Read Accesses .............................. 41 Read - Full-Page Burst ......................................................... 42 Read - DQM Operation ................................................ 43 Writes Write - Without Auto Precharge ................................ 44 Write - With Auto Precharge ...................................... 45 Alternating Bank Write Accesses .............................. 46 Write - Full-Page Burst ................................................. 47 Write - DQM Operation ............................................... 48 AS4SD4M16 AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SDRAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM 4 Meg x 16 SDRAM AS4SD4M16 CKE CLK CS WE CAS RAS CONTROL LOGIC COMMAND DECODE BANK1 BANK2 BANK3 MODE REGISTER REFRESH 12 COUNTER 12 1 2 ROW ADDRESS MUX 12 12 BANK0 ROWADDRESS LATCH & DECODER 4096 BANK 0 MEMORY ARRAY (4,096 X 256 X 16) SENSE AMPLIFIERS 4096 2 2 DQML, DQMH 16 DATA OUTPUT REGISTER 16 DQ0-DQ15 2 A0, A10, BA 14 ADDRESS REGISTER 2 BANK CONTROL LOGIC I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 256 (X16) COLUMN DECODER 16 DATA INPUT REGISTER 8 COLUMNADDRESS COUNTER/ LATCH 8 AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SDRAM Austin Semiconductor, Inc. PIN DESCRIPTION TSOP PIN NUMBERS 38 SYMBO