4 MEG x 16 DRAM

DRAM Austin Semiconductor, Inc. 4 MEG x 16 DRAM Extended Data Out (EDO) DRAM FEATURES • Single +3.3V ±0.3V power supply. • Industry-standard x16 pinout, timing, functions, and package. • 12 row, 10 column addresses • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • Extended Data-Out (EDO) PAGE MODE access • 4,096-cycle CAS-BEFORE-RAS (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention • Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020 AS4LC4M16 PIN ASSIGNMENT (Top View) 50-Pin TSOP (DG) OPTIONS • Package(s) 50-pin TSOP (400-mil) www.DataSheet4U.com • Timing 50ns access 60ns access • Refresh Rates Standard Refresh Self Refresh • Operating Temperature Ranges Military (-55°C to +125°C) Industrial (-40°C to +85°C) MARKINGS DG -5 -6 Configuration Refresh Row Address Column Addressing 4 Meg x 16 4K A0-A11 A0-A9 None S* XT IT NOTE: The symbol indicates signal is active LOW. *Contact factory for availability. Self refresh option available on IT version only. KEY TIMING PARAMETERS tRAC SPEED tRC -5 84ns 50ns -6 104ns 60ns tPC 20ns 25ns tAA 25ns 30ns tCAC 13ns 15ns tCAS 8ns 10ns For more products and information please visit our web site at www.austinsemiconductor.com AS4LC4M16 Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 DRAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM AS4LC4M16 AS4LC4M16 Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 DRAM Austin Semiconductor, Inc. GENERAL DESCRIPTION The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns. During READ or WRITE cycles, each location is uniquely addresses via the address bits: 12 row-address bits (A0 - A11) and 10 column-address bits (A0 - A9). In addition, both byte and word accesses are supported via the two CAS pins (CASL and CASH). The CAS functionality and timing related to address and control functions (e.g., latching column addresses or selecting CBR REFRESH) is such that the internal CAS signal is determined by the first external CAS signal (CASL or CASH) to transition LOW and the last to transition back HIGH. The CAS functionality and timing related to driving or latching data is such that each CAS signal independently controls the associated either DQ pins. AS4LC4M16 The row address is latched by the RAS signal, then the column address is latched by CAS. This device provides EDO-PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE or READ-MODIFY-WRITE) within a given row. The 4 Meg x 16 DRAM must be refreshed periodically in order to retain stored data. DRAM ACCESS Each location in the DRAM is uniquely addressable, as mentioned in the General Description. Use of both CAS signals resulted in a word access via the 16 I/O pins (DQ0 - DQ15). Using only one of the two signals results in a BYTE access cycle. CASL transitioning LOW selects an access cycle for the lower byte (DQ0 - DQ7), and CASH transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15). General byte and word access timing is shown in Figures 1 and 2. FIGURE 1: WORD and BYTE WRITE Example AS4LC4M16 Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 DRAM Austin Semiconductor, Inc. DRAM ACCESS (continued) A logic HIGH on WE dictates read mode, while a logic LOW on WE dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS (CASL or CASH), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE falls after CAS (CASL or CASH) is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE. During LATE WRITE or READ-MODIFYWRITE cycles, OE must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE LOW, no write will occur, and the data outputs will drive read data from the accessed location. Additionally, both bytes are active. A CAS precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are AS4LC4M16 not allowed during the same cycle. However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS precharge has been satisfied, are permissible. EDO PAGE MODE DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS. If CAS went HIGH and OE was LOW (active), the output buffers would be disabled. The 64MB EDO DRAM offers an accelerated page mode cycle by eliminating output disable from CAS HIGH. This option is called EDO, and it allows CAS precharge time (tCP) to occur without the output data going invalid (see READ and EDO-PAGE-MODE READ waveforms). EDO operates like any DRAM READ or FAST-PAGEMODE READ, except data is held valid after CAS goes HIGH, as long as RAS and OE are held LOW and WE is held HIGH. OE can be brought LOW or HIGH while CAS and RAS are LOW, and the DQs will transition between valid data and HighZ. Using OE, there are two methods to disable the outputs and FIGURE 2: WORD and BYTE READ Example AS4LC4M16 Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 DRAM Austin Semiconductor, Inc. FIGURE 3: OE Control of DQs AS4LC4M16 FIGURE 4: WE Control of DQs AS4LC4M16 Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 DRAM Austin Semiconductor, Inc. EDO PAGE MODE (Continued) two methods to disable the outputs and keep them disabled during the CAS HIGH time. The first method is to have OE HIGH when CAS transitions HIGH and keep OE HIGH for tOEHC thereafter. This will disable the DQs, and they will remain disabled (regardless of the state of OE after that point) until CAS falls again. The second method is to have OE LOW when CAS transitions HIGH and then bring OE HIGH for a minimum of tOEP anytime during the CAS HIGH period. This will disable the DQs, and they will remain disabled (regardless of the state of OE after that point) until CAS falls again (see Figure 3). During other cycles, the outputs are disabled at tOFF time after RAS and CAS are HIGH or at tWHZ after WE transitions LOW. The tOFF time is referenced from the rising edge of RAS or CAS, whichever occurs last. WE can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 4. EDO-PAGE-MODE operations are always initiated with a row address strobed in by the RAS signal, followed by a column address strobed in by CAS, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS while holding RAS LOW and entering new column addresses with each CAS cycle. Returning RAS HIGH terminates the EDO-PAGE-MODE operation. AS4LC4M16 DRAM REFRESH The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all rows in the 4 Meg x 16 DRAM array at least once every 64ms* (4,096 rows). The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms*. The DRAM refreshes one row for every CBR cycle. For this device, executing 4,096 CBR cycles will refresh the entire device. The CBR REFRESH will invoke the internal refresh counter for automatic RAS addressing. Alternatively, RAS-ONLY REFRESH capability is inherently provided. However, with this method, only one row is refreshed on each cycle. JEDEC strongly recommends the use of CBR REFRESH for this device. An optional self refresh mode is also available on the “S” version. The self refresh feature is initiated by performing a CBR Refresh cycle and holding RAS low for the specified tRASS. The “S” option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 31.25µs per cycle, when using a distributed CBR refresh. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh, however, if the controller is using RAS only or burst CBR refresh then a burst refresh using tRC (MIN) is required. NOTES: *64ms for IT version, 32ms for XT version. AS4LC4M16 Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 DRAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Relative to VSS .......................................-1V to +4.6V Voltage on NC, Inputs or I/O Pins Relative to VSS...................................................-1V to +4.6V Power Dissipation...........................................................................1W Operating temperature range, TA (ambient)..............-55°C to 125°C Storage temperature (plastic)......................................-55°C to