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• Organization: 2M×8 / 1M×16 • Sector architecture - One 16K; two 8K; one 32K; and thirty-one 64K byte sectors - One 8K; two 4K; one 16K; and thirty-one 32K word sectors - Boot code sector architecture—T (top) or B (bottom) - Erase any combination of sectors or full chip • Single 2.7-3.6V power supply for read/write operations • Sector protection • High speed 70/80/90/120 ns address access time • Automated on-chip programming algorithm - Automatically programs/verifies data at specified address • Automated on-chip erase algorithm - Automatically preprograms/erases chip or specified sectors • Hardware RESET pin - Resets internal state machine to read mode • Low power consumption - 200 nA typical automatic sleep mode current - 200 nA typical standby current - 10 mA typical read current • JEDEC standard software, packages and pinouts - 48-pin TSOP - 44-pin SO (availability TBD) • CFI (Common Flash Interface) compliant • Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit - RY/BY output • Erase suspend/resume - Supports reading data from or programming data to a sector not being erased • Low VCC write lock-out below 1.5V • 10 year data retention at 150C • 100,000 write/erase cycle endurance
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RY/BY VCC VSS RESET Program/erase control Command register CE OE Program voltage generator Chip enable Output enable Logic STB Data latch Sector protect/ erase voltage switches Erase voltage generator DQ0–DQ15 (A-1)
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48-pin TSOP
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE RESET NC NC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1
44-pin SO
Reset
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 WE A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
Input/output buffers
WE BYTE
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VCC detector
Timer
Address latch
STB
Y decoder
Y gating
X decoder
Cell matrix A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0
A0–A19
A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
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29LV160-70 Maximum access time Maximum chip enable access time Maximum output enable access time tAA tCE tOE 70 70 30 29LV160-80 80 80 30 29LV160-90 90 90 35 29LV160-120 120 120 50 Unit ns ns ns
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The AS29LV160 is a 16 megabit, 3.0 volt Flash memory organized as 2 Megabyte of 8 bits/1 Megabyte of 16 bits each. For flexible erase and program capability, the 8 megabits of data is divided into thirty-five sectors: one 16K, two 8K, one 32K, and thirty-one 64k byte sectors; or one 8K, two 4K, one 16K, and thirty-one 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16 data appears on DQ0–DQ15. The AS29LV160 is offered in JEDEC standard 48-pin TSOP, 48-pin BGA, and 44-pin SO (availability TBD) packages. This device is designed to be programmed and erased in-system with a single 3.0V VCC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29LV160 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word mode (×16 output) is selected by BYTE = high. Byte mode (×8 output) is selected by BYTE = low. The AS29LV160 is fully compatible with the JEDEC single power supply Flash standard. Write commands are sent to the command register using standard microprocessor write timings. An internal state-machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data from the device occurs in the same manner as other Flash or EPROM devices. Use the program command sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector (if it is not already programmed before executing the erase operation), times the erase pulse widths, and verifies proper cell margin. Boot sector architecture enables the system to boot from either the top (AS29LV160T) or the bottom (AS29LV160B) sector. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase operations in all, or any combination of, the nineteen sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The chip erase command will automatically erase all unprotected sectors. A factory shipped AS29LV160 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors. The device features single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and regulated voltages are provided for the Program and Erase operations. A low VCC detector automatically inhibits write operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase operations. The device automatically resets to the read mode after program/erase operations are completed. DQ2 indicates which sectors are being erased. The AS29LV160 resists accidental erasure or spurious programming signals resulting from power transitions. Control register architecture permits alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set to read mode with all program/erase commands disabled when VCC is less than VLKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate write commands, CE and WE must be logical zero and OE a logical 1. When the device’s hardware RESET pin is driven low, any program/erase operation in progress is terminated and the internal state machine is reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated on-chip program/erase algorithm, data in address locations being operated on may become corrupted and requires rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory. The AS29LV160 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programmed one at a time using EPROM programming mechanism of hot electron injection.
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Mode ID read MFR code ID read device code Read Standby Output disable Write Enable sector protect Sector unprotect Temporary sector unprotect Verify sector protect† Verify sector unprotect Hardware Reset
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CE L L L H L L L L X L L X
OE L L L X H H VID VID X L L X
WE H H H X H L Pulse/L Pulse/L X H H X
A0 L H A0 X X A0 L L X L L X
A1 L L A1 X X A1 H H X H H X
A6 L L A6 X X A6 L H X L H X
A9 VID VID A9 X X A9 VID VID X VID VID X
RESET H H H H H H H H VID H H L
DQ Code Code DOUT High Z High Z DIN X X X Code Code High Z
L = Low (VIH) = logic 1; VID = 10.0 ± 1.0V; X = don’t care. In ×16 mode, BYTE = VIH. In ×8 mode, BYTE = VIL with DQ8-DQ14 in high Z and DQ15 = A-1. †Verification of sector protect/unprotect during A9 = V ID.
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Item ID MFR code, device code Read mode Description Selected by A9 = VID(9.5V–10.5V), CE = OE = A1 = A6 = L, enabling outputs. When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (VIH), DOUT represents the device code for the AS29LV160. Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low and tOE after OE is low. Selected with CE = H. Part is powered down, and ICC reduced to <1.0 µA when CE = VCC ± 0.3V = RESET. If activated during an automated on-chip algorithm, the device completes the operation before entering standby. Part remains powered up; but outputs tri-stated with OE pulled high. Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands. Hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector protect algorithm on page 15.
Standby Output disable
Write
Enable sector protect
Disables sector protection for all sectors using external programming equipment. All sectors must be Sector unprotect protected prior to sector unpr
