5V 512K x 8 CMOS FLASH EEPROM

3UHOLPLQDU#LQIRUPDWLRQ ® $65<)373 89#845.ð;#&026#)ODVK#((3520 )HDWXUHV • Organization:512K words × 8 bits • Industrial and commercial temperature • Sector architecture - Eight 64K byte sectors - Erase any combination of sectors or full chip • Single 5.0±0.5V power supply for read/write operations • Sector protection • High speed 55/70/90/120/150 ns address access time • Automated on-chip programming algorithm - Automatically programs/verifies data at specified address • Automated on-chip erase algorithm - Automatically preprograms/erases chip or specified sectors • 10,000 write/erase cycle endurance • Low power consumption - 30 mA maximum read current - 60 mA maximum program current - 400 µA typical standby current • JEDEC standard software, packages and pinouts - 32-pin TSOP - 32-pin PLCC • Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit • Erase suspend/resume - Supports reading data from or programming data to a sector not being erased • Low VCC write lock-out below 2.8V )/$6+ )/$6+ )/$6+ )/$6+ /RJLF#EORFN#GLDJUDP VCC www.DataSheet4U.com 3LQ#DUUDQJHPHQW Sector protect switches Erase voltage generator DQ0–DQ7 A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 A7 A6 A5 A4 A3 A2 A1 VSS Input/output buffers AS29F040 WE Program/erase control Command register Program voltage generator Chip enable Output enable Logic STB Data latch 32-pin PLCC A12 A15 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 3 2 A16 A18 1 VCC WE 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE DQ7 A17 CE OE 32-pin TSOP Y gating VCC detector Timer Address latch STB Y decoder AS29F040 X decoder Cell matr A0 DQ0 A0–A18 6HOHFWLRQ#JXLGH AS29F040-55 Maximum access time Maximum chip enable access time Maximum output enable access time tAA 55 tCE 55 tOE 25 AS29F040-70 70 70 30 AS29F040-90 90 90 35 AS29F040-120 AS29F040-150 Unit 120 120 50 150 150 55 ns ns ns ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 4 Copyright ©2000 Alliance Semiconductor. All rights reserved. $65<)373 ® 3UHOLPLQDU#LQIRUPDWLRQ )XQFWLRQDO#GHVFULSWLRQ The AS29F040 is a 4-megabit, 5-volt-only Flash memory device organized as 512K bytes of 8 bits each. For flexible erase an program capability, the 4 megabits of data is divided into eight 64K-byte sectors. The ×8 data appears on DQ0–DQ7. The AS29F040 is offered in JEDEC standard 32-pin TSOP and 32-pin PLCC packages. This device is designed to be programmed an erased in-system with a single 5.0V VCC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29F040 offers access times of 55/70/90/120/150 ns, allowing 0-wait state operation of high-speed microprocessors. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls The AS29F040 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register use standard microprocessor write timings. An internal state machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data operates from the device in the same manner as other Flash or EPROM devices. The program command sequence is used to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin. The erase command sequence is used to invoke the automated on-chip erase algorithm that preprograms the sector if it is not already programmed before executing the erase operation, times the erase pulse widths, and verifies proper cell margin. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sector s. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase operations in any or all combinations of the eight sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from or program data to a sector that is not being erased. The chip erase command will automatically erase all unprotected sectors. A factory shipped AS29F040 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors. The device features single 5.0V power supply operation for read, write, and erase functions. Internally generated and regulate voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transtitions. DATA polling of DQ7 or toggle bit (DQ6) may be used to detect end-of-program or erase operations. The device automatically resets to read mode after program and/or erase operations are completed. The AS29F040 resists accidental erasure or spurious programming signals resulting from power transitions. Control register architecture permits the alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set to read mode with all program and/or erase commands disabled when VCC is less than V LKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical zero and OE a logical one to initiate write commands. The AS29F040 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programme one at a time using the EPROM programming mechanism of hot electron injection. )/$6+ 5 $//,$1&(#6(0,&21'8&725 ','#440533440$1#728233 0DUFK#5333 ® $65<)373 2SHUDWLQJ#PRGHV Mode ID read MFR code ID read device code Read Standby Output disable Write Enable sector protect Sector unprotect Verify sector protect CE L L L H L L L L L OE L L L X H H VID VID L WE H H H X H L Pulse/L Pulse/L H A0 L H A0 X X A0 L L L A1 L L A1 X X A1 H H H A6 L L A6 X X A6 L H L A9 VID VID A9 X X A9 VID VID VID DQ0-DQ7 Code Code DOUT High Z High Z DIN X X Code )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ )/$6+ L = Low (V IH); VID = 12.0 ± 0.5V; X = don’t car . 0RGH#GHILQLWLRQV Item ID MFR code, device code Read mode Description Selected by A9 = VID(11.5–12.5V), CE = OE = A1 = A6 = L, enabling outputs. When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (VIH), DOUT represents the device code for the AS29F040. Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low and tOE after OE is low. Selected with CE = H. Part is powered down, and ICC reduced to <1.0 mA for TTL input levels and <100 µA for CMOS levels. If activated during an automated on-chip algorithm, the device completes the operation before entering standby. Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of WE or CE, whichever occurs late . Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands. Hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. Disables sector protection for all sectors using external programming equipment. All sectors must be protected prior to sector unprotection. Verifies write protection for sector. Sectors are protected from program/erase operations on commercial programming equipment. Determine if sector protection exists in a system by writing the ID read command sequence and reading location XXX02h, where address bits A16–18 select the defined sector addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector. Standby Output disable Part remains powered up; but outputs disabled with OE pulled high. Write Enable sector protect Sector unprotect Verify sector protect ','#440533440$1#728233 $//,$1&(#6(0,&21'8&725 6 $65<)373 ® 3UHOLPLQDU#LQIRUPDWLRQ 6HFWRU#DUFKLWHFWXUH#DQG#DGGUHVV#WDEOH Equal sector architecture Sector Addresses 00000h–0FFFFh 10000h–1FFFFh 20000h–2FFFFh 30000h–3FFFFh 40000h–4FFFFh 50000h–5FFFFh 60000h–6FFFFh 70000h–7FFFFh Size (Kbytes) 64 64 64 64 64 64 64 64 A18 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ID sector address A17 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 )/$6+ 5($'#FRGHV Mode MFG code (Alliance Semiconductor) Device code Sector protection A18–A16 X X Sector address A9 VID VID VID A8–A7 X X Sector address A6 L L L A5–A2 X X Sector address A1 L L H A0 L H L Code on DQ0–DQ7 52h A4h 01h protected 00h unprotected L = Low (VIH); X = Don’t care. &RPPDQG#IRUPDW Command sequence Reset/read Reset/read Required bus cycles 1 4 1st bus write cycle Address XXXXh 5555h Data F0h AAh 2nd bus write cycle Address Read Address 2AAAh Data Read Data 55h 5555h F0h Read Address 00h MFR code Autoselect ID read 4 5555h AAh 2AAAh 55h 5555h 90h 01h Device code XXX02h Sector protection 4 6 6 1 1 5555h 5555h 5555h XXXXh XXXXh AAh AAh AAh B0h 30h 2AAAh 2AAAh 2AAAh 55h 55h 55h 5555h 5555h 5555h A0h 80h 80h Program Address 5555h 5555h Read Data 52h A4h 01 = protected 00 = unprotected Program Data AAh AAh 2AAAh 2AAAh 55h 55h 5555h Sector Address 10h 30h