Primary Side PWM Controller

Si LINK AS2916 Primary Side PWM Controller DESCRIPTION The AS2916 is a dual, full featured, pulse width modulation controller. The second controller is intended to run the auxiliary supply. Both controllers share common oscillator and power up logic. Based on an improved AS3842, the AS2916 provides additional features that reduce component count and improve specifications in a wide range of power supply designs. The added functionality also includes bulk voltage sensing, overvoltage input and soft start. The PWM function is controlled by the current sense comparator for normal current mode control and a second comparator for voltage mode soft start. A buffered RAMP signal is available for slope compensation without loading the oscillator. The output stage is a high current totem pole output that sees only 140 ns delay from the PWM comparators. The AS2916 requires less than 25 µA of startup current. The undervoltage lockout (UVLO) thresholds are nominally 13.5 V for turn on and 7.5 V for turn off. The oscillator discharge current is trimmed to provide guaranteed duty cycle clamping. The AS2916 has a second low frequency oscillator, which frequency modulates the operating frequency of the PWM by 25 %, thus reducing EMI emissions.. PINOUT OUTB VCC REG SNSB CMPB SS RAMP OSC PGND GND OUTA SNSA CMPA BOK ON WBL AS2916 AS2916 16L PDIP 16L SOIC PIN FUNCTION DESCRIPTION Pin Number 1 Function OUTB Description This is the gate drive output for the Main FET. The totem pole output has equivalent of an extra 10 Ω resistor to limit the FET turn on speed and a pull down reisistor to ensure the FET gate is never open. No external circuitry except for the FET is expected on this pin. The largest FET expected to be driven is IRFBC40. If a larger power FET is used, a buffer might be required. Positive supply for the IC. Absolute maximum rating is 20 V. The running voltage shall be provided by the Auxiliary convertor. Output of 5 V series regulator. This is the Main convertor current sense pin. An external RC filter from the Main power FET and slope compensation resistor from the RAMP pin is all the expected external circuitry. This is the Main output control pin. An opto isolated control signal from the secondary side error amplifier is buffered and connected to the invert pin of the main output current mode comparator. A pull-up current of 1 mA is provided so the only external circuitry expected is a common emitter optoisolator. This pin provides a 6 µA current source to linearly charge an external capacitor. This pin is compared to the RAMP pin in the soft start comparator, terminating output pulses when RAMP goes above the SS voltage. While this pin is held low, the main output is inhibited. This pin is a level-shifted and buffered oscillator waveform, used to provide slope compensation for the Main and Auxiliary converters. The pin also serves as the non-inverting input of the soft-start comparator. Oscillator frequency and maximum duty cycle are set by connecting a resistor (RT) to VREG and a capacitor (CT) to ground. Provides an FM modulation of the oscillator, approximately ± 25 % deviation frequency, at a modulation rate set by an external cap at WBL. Shorting to GND eliminates modulation. This pin is used to remotely turn the main convertor ON/OFF either for normal user application or for protection. Bulk OK. This is a brownout protection feature. The pin monitors the bulk voltage through a resistor divider. When BOK exceeds 2.5 V a 50 µA current is sourced from the pin for hysteresis. When the pin drops below 2.5 V the hysteresis is turned off and SS is pulled low, inhibiting the main output. The Auxiliary output is not tied to BOK and will run as long as there is sufficient bias voltage. 12 CMPA This is the Auxiliary convertor error amplifier compensation pin or if secondary controller is desired, the Auxiliary control input pin. A simple capacitor to ground is the only circuitry expected. Note: There is no external connection for voltage feedback. Voltage sensing is provided internally in such way that VCC is not loaded until it reaches predefined threshold. If secondary control is required, it can be forced into the CMPA pin. 13 SNSA This is the Auxiliary convertor current sense pin. An external RC filter from the Auxiliary power FET and slope compensation resistor from the RAMP pin is all the expected external circuitry. 2 3 4 VCC REG SNSB 5 CMPB 6 SS 7 RAMP 8 9 OSC WBL 10 11 ON BOK Silicon Link, Inc Pin Number 14 Function OUTA Description This is the gate drive output for the Auxiliary FET. The totem pole output has equivalent of an extra 33 Ω resistor to limit the FET turn on speed and a pull down reisistor to ensure the FET gate is never open. No external circuitry except for the FET is expected on this pin. The largest FET expected to be driven is IRF820. If a larger power FET is used, a buffer might be required. Signal ground. Power ground. 15 16 GND PGND ABSOLUTE MAXIMUM RATINGS Parameter Reference Current Output Current Supply Voltage Output Voltage Continuous Power Junction Temperature Storage Temperature Lead Temperature (soldering, 10 seconds) Symbol IREF IOUT VCC VOUT PD TJ TSTG TL Rating 200 1 20 20 500 150 -60 to 150 300 Unit mA A V V mW °C °C °C ELECTRICAL CHARACTERISTICS Electrical characteristics are guaranteed over the full junction temperature range (0-105 °C). Ambient temperature must be derated based upon power dissipation and package thermal characteristics. The conditions are: VCC = 15 V, BOK = 3 V, ON = 3 V, RT = 680 Ω, CT = 10 nF, and CWBL=2.2nF, unless otherwise stated. To override UVLO, VCC should be raised above UVLOhigh prior to test. Parameter 5 V Regulator Output Voltage Line Regulation Load Regulation Temperature Stability Total Output Variation Long-Term Stability Output Noise Voltage Maximum Source Current Silicon Link, Inc Symbol Test Condition Min Typ M a x Unit VREG PSRR IREG = 1 mA, TJ= 25° C 12 ≤ VCC ≤ 18 V 1≤ IREG ≤ 20mA 4.9 5.00 5 5 0.2 5.1 15 15 0.4 5.15 V mV mV mV/°C V mV µV TCREG Line, Load,Temperature Over 1,000 hrs at 25°C VNOISE IMAX 10 ≤ f ≤ 100kHz, TJ = 25°C VREG = 4.8 V 30 4.85 5 50 120 25 180 mA Oscillator Initial Frequency Voltage Stability Temperature Stability Amplitude Upper Trip Point Lower Trip Point Discharge Current Duty Cycle Limit TCf VOSC VH VL IDSC FOSC TJ= 25° C, VWBL= 0 V 8.5 ≤ VCC ≤ 18 V TMIN ≤ TJ ≤ TMAX VOSC peak-to-peak VWBL = 0 V VWBL= 0 V VOSC = 3 V RT = 680 Ω, CT = 10 nF, TJ = 25° TOT 7.5 46 117 132 0.2 5 1.55 2.8 1.25 8.7 50 9.5 54 143 1 kHz % % V V V mA % °C Over-Temperature Shutdown 140 Wobble Oscillator Wobble rate OSC Frequency Deviation Amplitude Upper Trip Point Lower Trip Point Charge Current Discharge Current FWBL DEV VWBL VH VL ICHRG IDSC VWBL = 0.7 V VWBL = 4.8 V -25 25 2.2 nF WBL to GND Change in main oscillator frequency VWBL peak-to-peak 3.4 +30 4.5 +40 1.8 2.7 0.9 -36 36 -50 50 6.0 +50 kHz kHz V V V µA µA Auxiliary PWM Comparator Input (CMPA) Regulation Voltage Transconductance Output Sink Current VCCREG Gm ICMPALow VCC = 16V, VCMPA = 1.1V 2 -0.5 5.4 13.4 14.5 1 6 -1.1 5.7 0.2 1.1 15.7 V mS mA mA V V Output Source Current ICMPAHigh VCC = 12V, VCMPA = 5V Output Swing High Output Swing Low VCMPAHigh VCC = 12V, ICMPA = 0.5mA VCMPALow VCC = 16V, ICMPA = 2mA Silicon Link, Inc Auxiliary Current Sense Comparator (SNSA) Transfer Gain CMPA Level Shift Current Sense Threshold Input Bias Current Propagation Delay to Output AVSNSA VLS VSNSA IBIAS tPD -0.2 ≤ VSNSA ≤ 0.8 V VSNSA = 0V VCMPA = 5V 0.95 3.00 1.5 1.05 -1 80 1.15 -10 150 V/V V V µA ns Main PWM Comparator Input (CMPB) Comp Source Current Comp Source Impedance Comp Swing High ICMPB ZCMPB VCMPBHigh VCMPB = 2.5V -1 10 5.4 -1.4 15 5.6 20 mA kΩ V Main Current Sense Comparator (SNSB) Transfer Gain CMPB Level Shift Current Sense Threshold Input Bias Current Propagation Delay to Output AVSNSB VLS VSNSB IBIAS tPD -0.2 ≤ VSNSB ≤ 0.8 V VSNSB = 0V VCMPB = 5V 0.95 3.00 1.5 1.05 -1 80 1.15 -10 150 V/V V V µA ns Soft Start Comparator SS charge current SS discharge current SS Lower Clamp Propagation Delay to Output RAMP High Level RAMP Low Level RAMP Levels TC ICharge SS VSS ≤ VRAMP IDsc SS VSS low tPB VRAMPH VRAMPL TJ = 25°C TJ = 25°C Note: RAMP waveform is same as OSC waveform, but level shifted down one diode drop IRAMPL IRAMPH TJ = 25°C TJ = 25°C 0.1 -2 2.0 0.45 VSS =1 V, VON < 1.5 V -4 2 -6 10 0.05 50 2.15 0.6 -2 0.2 100 2.3 0.75 -10 µA mA V ns V V mV/°C RAMP Sink Current RAMP Source Current 0.2 -10 mA mA Silicon Link, Inc Main Output Output Low Level Output Low Level Output High Level Output High Level On Resistance High Rise Time Fall Time Output Impedance to GND in UVLO State tR tF ZOUT CL = 1.3nF, 10%-90% CL = 1.3nF, 90%-10% VCC = 6 V VOUTBL VOUTBL VOUTBH VOUTBH ISINK = 10 mA ISINK = 150 mA ISOURCE = 10 mA, VCC= 15V ISOURCE = 150 mA, VCC = 15V 12 10 0.1 1.5 13 10.7 10 50 50 20 150 150 0.4 2.2 V V V V Ω ns ns kΩ Auxiliary Output Output Low Level Output Low Level Output High Level VOUTBL VOUTBL VOUTBH ISINK = 10 mA ISINK = 150 mA ISOURCE = 10 mA, VCC= 15V, VCMPA = 5V Output High Level VOUTBH ISOURCE = 110 mA, VCC =15V, VCMPA = 5V On Resistance High Rise Time Fall Time Output Impedance to GND in UVLO State tR tF ZOUT CL = 350 pF, 10%-90% CL = 350 pF, 90%-10% VCC = 6 V 33 70 50 20 150 150 Ω ns ns kΩ 7 8 V 12 0.1 1.5 13 0.4 2.2 V V V Under-Voltage Lockout Start-up Threshold Stop Threshold Start-up Current Operating Supply Current VCC (ON) VCC (OFF) ICC ICC VCC = 15 V 12.4 7 13.5 7.5 0.1 18 14.7 8 25 25 V V µA mA Silicon Link, Inc Housekeeping BOK UV threshold BOK UV Hysteresis Current BOK Input Bias Current ON Threshold ON Hysteresis ON Bias Current VBOK UV TJ= 25° C IHYST BOK VBOK = 2.6 V IBOK VON ∆VON IBIAS ON VON = 2.3 V VBOK = 2.4 V 2.35 -0.7 2.50 42 2.537 2.575 50 -0.1 2.5 -0.9 -0.5 58 -1 2.65 -1.1 -10 V µA µA V V µA Silicon Link, Inc VREG 50µA