N-Channel MOSFET

APT7M120B APT7M120S 1200V, 7A, 2.50Ω Max N-Channel MOSFET Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET. A proprietary planar stripe design yields excellent reliability and manufacturability. Low switching loss is achieved with low input capacitance and ultra low Crss "Miller" capacitance. The intrinsic gate resistance and capacitance of the poly-silicon gate structure help control slew rates during switching, resulting in low EMI and reliable paralleling, even when switching at very high frequency. Reliability in flyback, boost, forward, and other circuits is enhanced by the high avalanche energy capability. TO -2 47 D3PAK APT7M120B Single die MOSFET APT7M120S D G S FEATURES • Fast switching with low EMI/RFI • Low RDS(on) • Ultra low Crss for improved noise immunity • Low gate charge • Avalanche energy rated • RoHS compliant TYPICAL APPLICATIONS • PFC and other boost converter • Buck converter • Two switch forward (asymmetrical bridge) • Single switch forward • Flyback • Inverters www.DataSheet4U.com Absolute Maximum Ratings Symbol ID IDM VGS EAS IAR Parameter Continuous Drain Current @ TC = 25°C Continuous Drain Current @ TC = 100°C Pulsed Drain Current Gate-Source Voltage Single Pulse Avalanche Energy 2 Avalanche Current, Repetitive or Non-Repetitive 1 Ratings 7 4 28 ±30 575 3 Unit A V mJ A Thermal and Mechanical Characteristics Symbol PD RθJC RθCS TJ,TSTG TL WT Characteristic Total Power Dissipation @ TC = 25°C Junction to Case Thermal Resistance Case to Sink Thermal Resistance, Flat, Greased Surface Operating and Storage Junction Temperature Range Soldering Temperature for 10 Seconds (1.6mm from case) Package Weight 0.22 6.2 10 1.1 -55 0.11 150 300 Min Typ Max 335 0.37 Unit W °C/W °C oz g in·lbf N·m 12-2006 050-8104 Rev A Torque Mounting Torque ( TO-247 Package), 6-32 or M3 screw Microsemi Website - http://www.microsemi.com Static Characteristics Symbol VBR(DSS) ∆VBR(DSS)/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS TJ = 25°C unless otherwise specified Test Conditions VGS = 0V, ID = 250µA Reference to 25°C, ID = 250µA VGS = 10V, ID = 3A APT7M120B_S Typ 1.41 1.80 4 -10 Max Unit V V/°C Ω V mV/°C µA nA Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Drain-Source On Resistance 3 Min 1200 Gate-Source Threshold Voltage Threshold Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Source Leakage Current VGS = VDS, ID = 1mA VDS = 1200V VGS = 0V TJ = 25°C TJ = 125°C 3 2.50 5 100 500 ±100 VGS = ±30V Dynamic Characteristics Symbol gfs Ciss Crss Coss Co(cr) Co(er) Qg Qgs Qgd td(on) tr td(off) tf 4 TJ = 25°C unless otherwise specified Test Conditions VDS = 50V, ID = 3A VGS = 0V, VDS = 25V f = 1MHz Parameter Forward Transconductance Input Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance, Charge Related Min Typ 8 2565 31 190 75 Max Unit S pF 5 VGS = 0V, VDS = 0V to 800V Effective Output Capacitance, Energy Related Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Current Rise Time Turn-Off Delay Time Current Fall Time VGS = 0 to 10V, ID = 3A, VDS = 600V Resistive Switching VDD = 800V, ID = 3A RG = 4.7Ω 6 , VGG = 15V 38 80 13 37 14 8 45 13 nC ns Source-Drain Diode Characteristics Symbol IS ISM VSD trr Qrr dv/dt Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Peak Recovery dv/dt Test Conditions MOSFET symbol showing the integral reverse p-n junction diode (body diode) Min D Typ Max 7 Unit A G S 28 1.0 1165 18 10 V ns µC V/ns ISD = 3A, TJ = 25°C, VGS = 0V ISD = 3A, VDD = 100V 3 diSD/dt = 100A/µs, TJ = 25°C ISD ≤ 3A, di/dt ≤1000A/µs, VDD = 800V, TJ = 125°C 1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature. 2 Starting at TJ = 25°C, L = 127.78mH, RG = 4.7Ω, IAS = 3A. 3 Pulse test: Pulse Width < 380µs, duty cycle < 2%. 4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS. 5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of VDS less than V(BR)DSS, use this equation: Co(er) = -1.17E-7/VDS^2 + 1.42E-8/VDS + 2.01E-11. 6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452) Microsemi reserves the right to change, without notice, the specifications and information contained herein. 050-8104 Rev A 12-2006 25 V GS = 10V 8 7 APT7M120B_S T = 125°C J 20 ID, DRAIN CURRENT (A) TJ = -55°C V ID, DRIAN CURRENT (A) 6 5 4 3 2 1 0 0 GS = 6, 7, 8 & 9V 15 10 5V TJ = 25°C 5 TJ = 125°C 4.5V 0 TJ = 150°C 30 25 20 15 10 5 0 VDS(ON), DRAIN-TO-SOURCE VOLTAGE (V) Figure 1, Output Characteristics NORMALIZED TO VGS = 10V @ 3A 30 25 20 15 10 5 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 2, Output Characteristics RDS(ON), DRAIN-TO-SOURCE ON RESISTANCE 3.0 2.5 2.0 1.5 1.0 0.5 30 25 ID, DRAIN CURRENT (A) 20 15 10 5 0 VDS> ID(ON) x RDS(ON) MAX. 250µSEC. PULSE TEST @ <0.5 % DUTY CYCLE TJ = -55°C TJ = 25°C TJ = 125°C 0 25 50 75 100 125 150 0 -55 -25 TJ, JUNCTION TEMPERATURE (°C) Figure 3, RDS(ON) vs Junction Temperature 10 0 8 7 6 5 4 3 2 1 VGS, GATE-TO-SOURCE VOLTAGE (V) Figure 4, Transfer Characteristics 4,000 1,000 C, CAPACITANCE (pF) TJ = -55°C TJ = 25°C TJ = 125°C Ciss gfs, TRANSCONDUCTANCE 8 6 100 4 Coss 10 Crss 2 0 0 3 2 1 ID, DRAIN CURRENT (A) Figure 5, Gain vs Drain Current ID = 3A 4 800 1000 1200 600 400 200 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 6, Capacitance vs Drain-to-Source Voltage 0 30 ISD, REVERSE DRAIN CURRENT (A) 25 20 TJ = 25°C 1 16 VGS, GATE-TO-SOURCE VOLTAGE (V) 14 12 10 8 6 4 2 VDS = 240V VDS = 600V 15 TJ = 150°C VDS = 960V 10 5 0 050-8104 120 100 80 60 40 20 Qg, TOTAL GATE CHARGE (nC) Figure 7, Gate Charge vs Gate-to-Source Voltage 0 0 1.2 1.0 0.8 0.6 0.4 0.2 VSD, SOURCE-TO-DRAIN VOLTAGE (V) Figure 8, Reverse Drain Current vs Source-to-Drain Voltage 0 Rev A 12-2006 40 40 APT7M120B_S ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10 I DM 10 IDM Rds(on) 13µs 100µs 1ms 10ms 100ms 13µs 1 Rds(on) 100µs 1ms 1 10ms 100ms TJ = 150°C TC = 25°C DC line 0.1 TJ = 125°C TC = 75°C DC line 1 10 100 1200 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 9, Forward Safe Operating Area 0.1 Scaling for Different Case & Junction Temperatures: ID = ID(T = 25°C)*(TJ - TC)/125 C 10 100 1200 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 10, Maximum Forward Safe Operating Area 1 TJ (°C) 0.158 Dissipated Power (Watts) 0.00165 0.187 TC (°C) 0.214 ZEXT are the external thermal impedances: Case to sink, sink to ambient, etc. Set to zero when modeling only the case to junction. Figure 11, Transient Thermal Impedance Model 0.40 Z JC, THERMAL IMPEDANCE (°C/W) θ 0.35 0.30 0.25 0.20 0.15 0.3 0.7 D = 0.9 0.5 ZEXT Note: PDM t1 t2 0.10 0.05 0 10-5 0.1 0.05 SINGLE PULSE Duty Factor D = 1/t2 Peak TJ = PDM x ZθJC + TC t1 = Pulse Duration t 10-3 10-2 10-1 RECTANGULAR PULSE DURATION (seconds) Figure 12. Maximum Effective Transient Thermal Impedance Junction-to-Case vs Pulse Duration 10-4 1.0 TO-247 (B) Package Outline e3 100% Sn Plated 15.49 (.610) 16.26 (.640) 5.38 (.212) 6.20 (.244) D3PAK Package Outline Drain (Heat Sink) 4.98 (.196) 5.08 (.200) 1.47 (.058) 1.57 (.062) 15.95 (.628) 16.05(.632) 13.41 (.528) 13.51(.532) 4.69 (.185) 5.31 (.209) 1.49 (.059) 2.49 (.098) 6.15 (.242) BSC 1.04 (.041) 1.15(.045) Drain 20.80 (.819) 21.46 (.845) 3.50 (.138) 3.81 (.150) Revised 4/18/95 13.79 (.543) 13.99(.551) Revised 8/29/97 11.51 (.453) 11.61 (.457) 0.46 (.018) 0.56 (.022) {3 Plcs} 12-2006 4.50 (.177) Max. 0.40 (.016) 0.79 (.031) 2.87 (.113) 3.12 (.123) 1.65 (.065) 2.13 (.084) 19.81 (.780) 20.32 (.800) 0.020 (.001) 0.178 (.007) 2.67 (.105) 2.84 (.112) 1.27 (.050) 1.40 (.055) 1.98 (.078) 2.08 (.082) 5.45 (.215) BSC {2 Plcs.} 1.22 (.048) 1.32 (.052) 3.81 (.150) 4.06 (.160) (Base of Lead) Rev A 1.01 (.040) 1.40 (.055) Gate Drain Source Heat Sink (Drain) and Leads are Plated 2.21 (.087) 2.59 (.102) 050-8104 5.45 (.215) BSC 2-Plcs. Dimensions in Millimeters and (Inches) Source Drain Gate Dimensions in Millimeters (Inches) Microsemi's products are covered by one or more of U.S.patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 and foreign patents. US and Foreign patents pending. All Rights Reserved.