74F Extended Octal-Plus Family Applications

INTEGRATED CIRCUITS AN214 74F extended octal-plus family applications June 1988 (Revised June 1996) Philips Semiconductors Philips Semiconductors Application note 74F extended octal-plus family applications AN214 74F Extended Octal-Plus Family Features • 8-, 9-, and 10-bit “Light-Load” bus products – Buffers/Drivers With and without latches or registers With and without 8-bit parity checker/generator – Transceivers With and without dual registers With and without 8-bit parity checker/generator “light-load” inputs, “broadside” design and high functional density/performance of the family make this product line ideal for buffering the limited drive capabilities of standard, custom and semicustom MOS VLSI devices to the rigorous environments of today’s leading edge high performance logic designs. The family also is an excellent choice for all general interface applications. “Flow-Through” Design The “flow-through” or “broadside” chip layout/package design is illustrated in Figure 1 showing the block diagrams and pin configurations of the 74F828 10-bit Inverting buffer. Note that all of these “broadside” designs allow logic signals to flow into one side and out of the other without crossing or folding back on signal paths such as the 74F240 Octal Buffers (Figure 2). If you compare the physical layout requirements of the path of PC board bus lines for the 74F828 to that of the 74F240’s “zig-zag” path, you will see the significant advantages of the 74F Extended Octal-Plus Family’s “flow-through” design in simplifying the design and layout of large, high density, bus-oriented PC boards. • Patented “Light-Load” inputs: – Input Current = ±20µA per input – Transceiver I/O pins = ±70µA • High performance output drive currents: – IOL = 64mA/48mA @ ±5%/10% VCC • “Flow-through” or “broadside” I/O pin configuration • Ideal for MOS CPU, peripherals and semi-custom bus interface • 24-pin, 300mil-wide, plastic slim-DIPs • High performance buffers — tP(max) = 7.5ns • High performance latches/registers — fT = 100MHz Introduction The 74F Extended Octal-Plus Family incorporates all of the latest Philips Semiconductors octal, 9-bit and 10-bit buffer, transceiver, latch and register functions. all devices in this family utilize the Philips Semiconductors patented “Light-Load” NPN, ±20µA input current structure and have “flow-through” or “broadside” input/output pin configurations where the inputs and outputs are lined-up on opposite sides of a standard 24-pin Slim-DIP package. The – IOH = –15mA/–3mA @ ±5%/10% VCC The 24-pin, 300mil-wide, Slip-DIP Solution With the advent of advanced Schottky TTL technology came the ability to significantly increase the functional density of standard logic building blocks. However, not until the development of the 24-pin, 300mil-wide, Slim-DIP package was it possible to take full advantage of these new chip densities. The entire family provides significant advantages in package count, pin count and packing density when compared to older technologies. Further density enhancements can be achieved by using Philips surface mounted packages. By combining high functional density into a 24-pin 300mil-wide Slim-DIP package, the Philips Semiconductors 74F Extended Octal-Plus Family allows the reduction of PC board parts count and cost while optimizing layout with “broadside” chip designs, reducing total system power dissipation and increasing system reliability. OE0 D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 24 VCC 23 O0 22 O1 21 O2 20 O3 19 O4 18 O5 17 O6 16 O7 15 O8 14 O9 13 OE1 OEa Ia0 Yb0 Ia1 Yb1 Ia2 Yb2 Ia3 Yb3 1 2 3 4 5 6 7 8 9 20 VCC 19 OEb 18 Ya0 17 Ib0 16 Ya1 15 Ib1 14 Ya2 13 Ib2 12 Ya3 11 Ib3 D8 10 D9 11 GND 12 GND 10 SF01329 SF01330 Figure 1. 74F828 Broadside Pin Configuration Figure 2. 74F240 ’Zig-Zag” Pin Configuration June 1988 2 Revised: June 1996 Philips Semiconductors Application note 74F extended octal-plus family applications AN214 EN VCC D5 D6 R1 6K R9 2.8K R10 2.8K D9 D8 D4 Q8 D3 D7 R5 5K Q4 R6 6K R7 7.5K Q6 Q5 R2 50 R3 10K R4 50 R8 2K Q7 R12 500 D11 R13 10K Q9 Q10 D10 R11 2.8K Q12 D13 R14 Q13 YOUT YIN Q1 Q1A Q2 Q11 D1 D2 Q3 D12 IOLoptions: 1) If IOH/IOL R14 R11 R10 R12 2) If IOH/IOL R14 R11 R10 R12 = = = = = = = = = = –15/64 12 2.8K 2.8K 500 –3/24 30 5K 5K 2K mA Ω Ω Ω Ω mA Ω Ω Ω Ω SF01331 Figure 3. 74F455 Buffer/Drive Cell Circuit Diagram The 8-, 9-, and 10-bit Series 24-pin Solution Whether your system requires an 8–, 9-, or 10-bit bus interface, the Extended Octal-Plus Family has standardized solutions in 24-pin/Slim-DIP/Broadside input/output packages with corner power supply pins (12 & 24) and standard designations for common control functions located at or near the package corners. Octals offer more mode control inputs than do the 9- or 10-bit products. Virtually all family devices with 3-State outputs are guaranteed to source/sink –15/64mA @ VOH/VOL = 2.0/0.55V (except for the 74F841–846 Latched Drivers, which are spec’ed at –15mA/48mA). The AN port outputs of several of the family’s transceivers are guaranteed to supply –3mA/48mA). The Octal Parity Bus Series offers several notable exceptions to the above standard pinouts. This series has three parts with two center-package ground pins to minimize ground-bounce noise. All outputs (except the AN port of the 74F657 Parity Bus Transceiver spec’ed at –3mA/24mA) are guaranteed to source/sink more than –15mA/64mA. Current PC board, multi-layer technology make is possible to take into consideration the physical location of input/output pins, transmission line characteristics and supply power distribution. Lining up all inputs and output on opposite sides of the package allows the address, data and control bus signal to flow in a direct physical path from the µP CPU through the bus interface chips and onto the appropriate bus. This “broadside” bus design approach produces very clean PC board layouts and may, in fact eliminate and entire PC board interconnection layer. Standardization of power supply, mode control and input/output pins, whether 8-, 9-, or 10-bit bus functions, permits simplified, structured PC board layout. Input Structures Referring to Figure 3, the 74F455 Inverting Buffer/Driver Cell Circuit Diagram is an example of the family’s input and output circuitry. The patented Philips Semiconductors “Light-Load” NPN input structure (Q1/23/4/5, R1/2/3/4/5/6 and D4) and turn-OFF speed-up circuit (Q2 and D2/3) are used throughout the 74F Extended Octal-Plus Family. the “Light-Load” NPN input is actually a high speed, differential amplifier with the reference side, the anode of D4, clamped at two diode voltage drops above ground (BE junctions of Q8/9/10 and Q 11 of 1.4V at 25°C). When the VIH rises above this clamp voltage, the BE junction of Q1 is forward based allowing beta amplified, CE current to flow into the <1.0mA constant current source, Q3 (driven by Q4/5 and R2/3/4/5/6). The beta of Q1 is guaranteed, by design, to be >50, thereby guaranteeing that the input base bias current will be <20µA. The emitter of Q1 rises to 1VBE (300mV) below the VIH, reverse biasing D4 and permitting C8/9/10 base bias current to flow through R1. The patented turn-OFF circuit consisting of Q2 and D2/3 produces a dynamic speed to help turn Q8/9/10 OFF quickly. During the time that the Q1 is turned-ON (input = VIH >2.0V), the revers-biased Schottky diode, D2, acting as a capacitor, will be charged to the voltage at the emitter of Q1A or 1VBE voltage drop below the input (>2.0 – 1VBE). When the input is switched to