Field Programmable Analog Array

AN10E40 Field Programmable Analog Array The AN10E40 brings to analog what FPGAs brought to digital; extremely rapid production and prototype circuit realization with field re-programmability. The AN10E40 consists of a 4 x 5 matrix of fully configurable switched capacitor cells, enmeshed in a fabric of programmable interconnect resources. These programmable features are directed by an on-chip SRAM configuration memory. The SRAM configuration memory is initialized on power up via an off chip serial PROM or through the AN10E40Õs standard microprocessor peripheral interface. A configuration memory image is easily constructed using the companion AnadigmDesigner¨ software which includes an extensive library of adjustable, proven, pre-built functions. The configurable analog blocks are often consumed one at a time, though some of the more complex library functions may consume two or more blocks. Specialized IO cells surround the core to bring your analog signals in and out of the array. The AN10E40 coupled with the intuitive AnadigmDesigner¨ software gives both digital and analog designers a competitive advantage in designing analog circuits that canÕt really be compared to any other design system in existence. Quickly constructed, accurate, drift free, temperature compensated and programmable analog circuits are now yours. Imagine the power of programmable with the versatility of analog. Benefits • • • • • • Extremely Rapid Analog Design Ð Minutes not weeks to re-spin a new design idea In Circuit Programmable Ð Behavior can be changed as fast as 125 microseconds Re-Configurable Using Conventional Logic, Serial PROMs or Microcontrollers Extremely Stable over Voltage and Temperature • Flexible Internal Clock and Routing Resources No Component Aging • No More Trimming Components Reliable and Repeatable Performance • No More Tuning Components Config. Logic I w w X Y Z X Y Z w I .D CAB CAB CAB O Y Z I O I O I O X CAB CAB CAB CAB Y O Z X CAB CAB CAB CAB Y Z X CAB CAB CAB CAB Y Z X CAB t a CAB CAB CAB CAB Y S a e h U t4 e .c m o O Z Vref I X Y O Z I X Y O Z I X Y O Z I X Y O Z X Anadigm¨ UM020800-U005 www.DataSheet4U.com A B C I O I O I O I X Y Z X Y Z Configuration Data Shift Register Anadigm¨ reserves the right to make any changes without further notice to any products herein. Anadigm¨ makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Anadigm¨ assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including with limitation consequential or incidental damages. ÒTypicalÓ parameters can and do vary in different applications. All operating parameters, including ÒTypicalsÓ must be validated for each customer application by customerÕs technical experts. Anadigm¨ does not convey any license under its patent rights nor the rights of others. Anadigm¨ products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Anadigm¨ product could create a situation where personal injury or death may occur. Should buyer purchase or use Anadigm¨ product for any such unintended or unauthorized application, buyer shall indemnify and hold Anadigm¨ and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Anadigm¨ was negligent regarding the design or manufacture of the part. Copyright © Anadigm¨ 2002 All Rights Reserved Anadigm¨ UM020800-U005 AN10E40 Data Manual Table of Contents i Features of AN10E40 ...................................................................................................................................................... 1 Available IPmodule Functions ......................................................................................................................................... 1 How It Works .................................................................................................................................................................... 1 AN10E40 Architecture ..................................................................................................................................................... 2 The Configurable Analog Block....................................................................................................................................... 3 A Quick Review of Switched Capacitor Circuits ......................................................................................................... 3 CAB Details .................................................................................................................................................................. 4 Routing Resources........................................................................................................................................................... 4 Clock Generation ............................................................................................................................................................. 4 Voltage Reference ........................................................................................................................................................... 5 Voltage Mid-Rail Generator ............................................................................................................................................. 5 Analog Input Output Cell.................................................................................................................................................. 6 Sallen Key Filtering ...................................................................................................................................................... 6 nd 2 Order Sallen-Key Filter for Output Smoothing ...................................................................................................... 7 th 4 Order Sallen-Key Filter for Output Smoothing ....................................................................................................... 7 nd 2 Order Sallen-Key Filter for Input Anti-Aliasing ...................................................................................................... 7 th 4 Order Sallen-Key Filter for Input Anti-Aliasing ....................................................................................................... 8 Configuration Engine ....................................................................................................................................................... 9 Mode 0 Ð Micro Mode (Parallel Loading) .................................................................................................................. 10 Micro Mode Maximum Data Transfer Rate ........................................................................................................... 12 Function Register (RS=0) and Data/Status Register (RS=1) ............................................................................... 12 Sending the Reset Device Command ................................................................................................................... 12 Micro Mode - Configuration Sequence .................................................................................................................. 13 Organization of Configuration Memory - The ASCII Hex Configuration File Format .......................................... 14 Mode 1 Ð Boot from ROM (BFR Mode)..................................................................................................................... 15 BFR Timing................................................................................................................................................................. 16 Configuration Clock .................................................................................................................................................... 17 Reset Sequences........................................................................................................................................................... 18 Analog Power On Reset (APOR) & Power On Reset (POR) ................................................................................... 18 Internal Reset Activity................................................................................................................................................. 18 External Reset Assertion............................................................................................................................................ 18 Mechanical ..................................................................................................................................................................... 18 Package Details.......................................................................................................................................................... 18 Pin Out Description .................................................................................................................................................... 19 Package Pin Electrical Characterization ................................................................................................................... 22 Powers, Grounds and Bypassing .................................................................................................................................. 22 Recommended Configuration for Power & Ground .........