Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM

PRELIMINARY Am42DL32x4G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features ■ Power supply voltage of 2.7 to 3.3 volt ■ High performance — Flash Access time as fast as 70 ns — SRAM access time as fast as 55 ns SOFTWARE FEATURES ■ Data Management Software (DMS) — AMD-supplied software manages data programming and erasing, enabling EEPROM emulation — Eases sector erase limitations ■ Package — 73-Ball FBGA ■ Supports Common Flash Memory Interface (CFI) ■ Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank ■ Operating Temperature — –40°C to +85°C ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles Flash Memory Features ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Secured Silicon (SecSi) Sector: Extra 256 Byte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. — Customer lockable: Sector is one-time programmable. Once locked, data cannot be changed ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to reading array data ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero ■ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing ■ Top or bottom boot block ■ Manufactured on 0.17 µm process technology ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system PERFORMANCE CHARACTERISTICS ■ High performance — Access time as fast as 70 ns — Program time: 4 µs/word typical utilizing Accelerate function SRAM Features ■ Power dissipation — Operating: 22 mA maximum for 70 ns, 30 mA maximum for 55 ns — Standby: 10 µA maximum ■ Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode ■ Minimum 1 million write cycles guaranteed per sector ■ 20 Year data retention at 125°C — Reliable operation for the life of the system ■ ■ ■ ■ CE1s# and CE2s Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: 1.5 to 3.3 volt Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8) This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 25822 Rev: B Amendment/0 Issue Date: May 19, 2003 Refer to AMD’s Website (www.amd.com) for the latest information. PRELIMINARY GENERAL DESCRIPTION Am29DL32xG Features The Am29DL322G/323G/324G consists of 32 megabit, 3.0 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The devices are available with access times of 85 and 70 ns. The device is offered in a 73-ball FBGA package. Standard control pins—chip enable (CE#f), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The devices requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is a n a d va n t a g e co m p a r e d t o sys t e ms w h e r e user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memo r y. T h i s c a n b e a c h i e v e d i n - s y s t e m o r v i a programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL32xG device family uses multiple bank architectures to provide flexibility for different applications. Three devices are available with the following bank sizes: Device DL322 DL323 DL324 Bank 1 4 8 16 Bank 2 28 24 16 The Secured Silicon (SecSi) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number). Customer Lockable devices are one-time programmable and one-time lockable. 2 Am42DL32x4G May 19, 2003 PRELIMINARY TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7 Special Handling Instructions for FBGA Package .................... 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10 Table 2. Device Bus Operations—Flash Byte Mode, CIOf = VSS ....12 Figure 6. Toggle Bit Algorithm........................................................ 34 DQ2: Toggle Bit II ................................................................... 35 Reading Toggle Bits DQ6/DQ2 ............................................... 35 DQ5: Exceeded Timing Limits ................................................ 35 DQ3: Sector Erase Timer ....................................................... 35 Table 18. Write Operation Status ................................................... 36 Requirements for Reading Array Data ................................... 13 Writing Commands/Command Sequences ............................ 13 Accelerated Program Operation ............................................. 13 Autoselect Functions .............................................................. 13 Simultaneous Read/Write Operations with Zero Latency ....... 13 Automatic Sleep Mode ........................................................... 14 RESET#: Hardware Reset Pin ........