Page Mode Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM

Am41PDS3228D Data Sheet -XO  7KH IROORZLQJ GRFXPHQW VSHFLILHV 6SDQVLRQ PHPRU SURGXFWV WKDW DUH QRZ RIIHUHG E ERWK $GYDQFHG 0LFUR 'HYLFHV DQG )XMLWVX $OWKRXJK WKH GRFXPHQW LV PDUNHG ZLWK WKH QDPH RI WKH FRPSDQ WKDW RULJ LQDOO GHYHORSHG WKH VSHFLILFDWLRQ WKHVH SURGXFWV ZLOO EH RIIHUHG WR FXVWRPHUV RI ERWK $0' DQG )XMLWVX Continuity of Specifications 7KHUH LV QR FKDQJH WR WKLV GDWDVKHHW DV D UHVXOW RI RIIHULQJ WKH GHYLFH DV D 6SDQVLRQ SURGXFW $Q FKDQJHV WKDW KDYH EHHQ PDGH DUH WKH UHVXOW RI QRUPDO GDWDVKHHW LPSURYHPHQW DQG DUH QRWHG LQ WKH GRFXPHQW UHYLVLRQ VXPPDU ZKHUH VXSSRUWHG )XWXUH URXWLQH UHYLVLRQV ZLOO RFFXU ZKHQ DSSURSULDWH DQG FKDQJHV ZLOO EH QRWHG LQ D UHYLVLRQ VXPPDU Continuity of Ordering Part Numbers $0' DQG )XMLWVX FRQWLQXH WR VXSSRUW H[LVWLQJ SDUW QXPEHUV EHJLQQLQJ ZLWK ³$P´ DQG ³0%0´ 7R RUGHU WKHVH SURGXFWV SOHDVH XVH RQO WKH 2UGHULQJ 3DUW 1XPEHUV OLVWHG LQ WKLV GRFXPHQW For More Information 3OHDVH FRQWDFW RXU ORFDO $0' RU )XMLWVX VDOHV RIILFH IRU DGGLWLRQDO LQIRUPDWLRQ DERXW 6SDQVLRQ PHPRU VROXWLRQV Publication Number 26014 Revision A Amendment +1 Issue Date May 13, 2003 PRELIMINARY Am41PDS3228D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features ■ Power supply voltage of 1.8 to 2.2 volt ■ High performance — Access time as fast as 100 ns flash, 70 ns SRAM — — — — 24 mA active read current at 10 MHz for initial page read 0.5 mA active read current at 10 MHz for intra-page read 1 mA active read current at 20 MHz for intra-page read 200 nA in standby or automatic sleep mode ■ Package — 73-Ball FBGA ■ Minimum 1 million write cycles guaranteed per sector ■ 20 year data retention at 125°C — Reliable operation for the life of the system ■ Operating Temperature — –40°C to +85°C SOFTWARE FEATURES ■ Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations Flash Memory Features ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank. — Zero latency between read and write operations ■ Erase Suspend/Erase Resume ■ Data# Polling and Toggle Bits ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences ■ Page Mode Operation — 4 word page allows fast asynchronous reads ■ Dual Bank architecture — One 4 Mbit bank and one 28 Mbit bank HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) ■ Hardware reset pin (RESET#) ■ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing ■ SecSi (Secured Silicon) Sector: Extra 64 KByte sector — Factory locked and identifiable: 16 byte Electronic Serial Number available for factory secure, random ID; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. ■ Top or bottom boot block ■ Manufactured on 0.23 µm process technology ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard SRAM Features ■ Power dissipation — Operating: 2 mA typical — Standby: 0.5 µA typical PERFORMANCE CHARACTERISTICS ■ High performance — Random access time of 100 ns at 1.8 V to 2.2 V VCC ■ Ultra low power consumption (typical values) — 2.5 mA active read current at 1 MHz for initial page read ■ ■ ■ ■ CE1s# and CE2s Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: 1.0 to 2.2 volt Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8) This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 26104 Rev: A Amendment/+1 Issue Date: May 13, 2002 Refer to AMD’s Website (www.amd.com) for the latest information. PRELIMINARY GENERAL DESCRIPTION The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash memory organized as 2,097,152 words of 16 bits each. The device is designed to be programmed in system with standard system 1.8 V VCC supply. This d evice ca n a lso be re prog ra mm ed in stand ard EPROM programmers. The Am29PDS322D offers fast page access time of 40 ns with random access time of 100 ns (at 1.8 V to 2.2 V VCC), allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The page size is 4 words. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is a n a d v a n t a g e c o m p a re d to sy st e m s w h e re user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. Th e system can also place the de vice into the standby mode. Power consumption is greatly reduced in both modes. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: Bank 1 Sectors Quantity 8 7 Size 4 Kwords 56 32 Kwords 4 Mbits total 28 Mbits total 32 Kwords Bank 2 Sectors Quantity Size Am29PDS322D Features The SecSi (Secured Silicon) Sector is an extra 64 KByte sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any 2 Am41PDS3228D May 13, 2002 PRELIMINARY TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 7 Pin Description . . . . . . . . . . . . . . . . . . . .