Uniform Sector Flash Memory

Am29F017D Data Sheet RETIRED PRODUCT This product has been retired and is not recommended for designs. Please contact your Spansion representative for alternates. Availability of this document is retained for reference and historical purposes only. The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 21195 Revision E Amendment 6 Issue Date September 12, 2006 THIS PAGE LEFT INTENTIONALLY BLANK. DATA SHEET Am29F017D 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory This product has been retired and is not recommended for designs. Please contact your Spansion representative for alternates. Availability of this document is retained for reference and historical purposes only. DISTINCTIVE CHARACTERISTICS Optimized for memory card applications — Backwards-compatible with Am29F016C and Am29F017B 5.0 V ± 10%, single power supply operation — Minimizes system level power requirements Manufactured on 0.23 µm process technology High performance — Access times as fast as 70 ns Low power consumption — 25 mA typical active read current — 30 mA typical program/erase current — 1 µA typical standby current (standard access time to active mode) Flexible sector architecture — 32 uniform sectors of 64 Kbytes each — Any combination of sectors can be erased. — Supports full chip erase — Group sector protection: A hardware method of locking sector groups to prevent any program or erase operations within that sector group Temporary Sector Group Unprotect allows code changes in previously locked sectors Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies bytes at specified addresses Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences Minimum 1,000,000 program/erase cycles per sector guaranteed 20-year data retention at 125°C — Reliable operation for the life of the system Package options — 40-pin TSOP — 48-pin TSOP Compatible with JEDEC standards — Pinout and software compatible with single-power-supply Flash standard — Superior inadvertent write protection Data# Polling and toggle bits — Provides a software method of detecting program or erase cycle completion Ready/Busy# output (RY/BY#) — Provides a hardware method for detecting program or erase cycle completion Erase Suspend/Erase Resume — Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation Hardware reset pin (RESET#) — Resets internal state machine to the read mode This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21195 Rev: E Amendment: 5 Issue Date: September 12, 2006 D A T A S H E E T GENERAL DESCRIPTION The Am29F017D is a 16 Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes. The 8 bits of data appear on DQ0–DQ7. The Am29F017D is offered in a 40-pin or 48-pin TSOP package. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMD’s 0.23 µ m process technology, and offers all the features and benefits of the 0.32 µm Am29F017B and the 0.5 µm Am29F016C. The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. 2 Am29F017D 21195E5 September 12, 2006 D A T A S H E E T TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . Device Bus Operations . . . . . . . . . . . . . . . . . . . . . Requirements for Reading Array Data ..................................... Writing Commands/Command Sequences .............................. Program and Erase Operation Status ...................................... Standby Mode .......................................................................... RESET#: Hardware Reset Pin ................................................. Output Disable Mode................................................................ 4 4 5 5 5 6 7 7 7 7 8 8 8 DQ6: Toggle Bit I .................................................................... DQ2: Toggle Bit II ................................................................... Reading Toggle Bits DQ6/DQ2............................................... DQ5: Exceeded Timing Limits ................................................ DQ3: Sector Erase Timer ....................................................... 20 20 20 21 21 Figure 5. Toggle Bit Algorithm........................................................ 21 Table 10. Write Operation Status................................................... 22 Table 1. Am29F017D Device Bus Operations .................................. 7 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 23 Figure 6. Maximum Negative Overshoot Waveform ...................... 23 Figure 7. Maximum Positive Overshoot Waveform........................ 23 Table 2. Sector Address Table.......................................................... 9 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 TTL/NMOS Compatible .......................................................... 24 CMOS Compatible.................................................................. 24 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 8. Test Setup...................................................................... 25 Table 11. Test Specifications ......................................................... 25 Autoselect Mode..................................................................... 10 Table 3. Am29F017D Autoselect Codes (High Voltage Me