(ADS6442 - ADS6445) ADC

ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531 – MAY 2007 QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS FEATURES • • • • Maximum Sample Rate: 125 MSPS 14-Bit Resolution with No Missing Codes Simultaneous Sample and Hold 3.5dB Coarse Gain and up to 6dB Programmable Fine Gain for SFDR/SNR Trade-Off Serialized LVDS Outputs with Programmable Internal Termination Option Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVPP Internal Reference with External Reference Support No External Decoupling Required for References 3.3-V Analog and Digital Supply • • • 64 QFN Package (9 mm × 9 mm) Pin Compatible 12-Bit Family (ADS642X SLAS532) Feature Compatible Dual Channel Family (ADS624X - SLAS542, ADS644X - SLAS543) APPLICATIONS • • • • Base-Station IF Receivers Diversity Receivers Medical Imaging Test Equipment Table 1. ADS64XX Quad Channel Family 125 MSPS ADS644X 14 Bit ADS642X 12 Bit ADS6445 ADS6425 105 MSPS ADS6444 ADS6424 80 MSPS ADS6443 ADS6423 65 MSPS ADS6442 ADS6422 • • • • • Table 2. Performance Summary www.DataSheet4U.com ADS6445 SFDR, dBc SINAD, dBFS Fin = 10MHz (0 dB gain) Fin = 170MHz (3.5 dB gain) Fin = 10MHz (0 dB gain) Fin = 170MHz (3.5 dB gain) 87 79 73.4 68.3 420 ADS6444 91 83 73.4 69.3 340 ADS6443 92 84 74.2 69.4 300 ADS6442 93 84 74.3 70 265 Power, per channel, mW DESCRIPTION The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB. The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies. An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver. The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The ADS644X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C). AVDD AGND LVDD LGND CAP BIT Clock CLKP CLKM DCLKP DCLKM PLL FRAME Clock FCLKP FCLKM DA0_P DA0_M DA1_P DA1_M DB0_P DB0_M DB1_P DB1_M DC0_P DC0_M DC1_P DC1_M DD0_P DD0_M DD1_P DD1_M INA_P SHA INA_M 14-Bit ADC Digital Encoder and Serializer INB_P SHA INB_M 14-Bit ADC Digital Encoder and Serializer INC_P SHA INC_M 14-Bit ADC Digital Encoder and Serializer IND_P SHA IND_M 14-Bit ADC Digital Encoder and Serializer VCM ADS644x Reference REFM REFP Parallel Interface Serial Interface CFG1 PDN CFG2 CFG3 CFG4 SEN RESET SDATA SCLK B0199-03 2 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR RGC RGC RGC RGC SPECIFIED TEMPERATURE RANGE –40°C to 85°C –40°C to 85°C –40°C to 85°C –40°C to 85°C PACKAGE MARKING AZ6445 AZ6444 AZ6443 AZ6442 (1) ORDERING NUMBER ADS6445IRGCT ADS6445IRGCR ADS6444IRGCT ADS6444IRGCR ADS6443IRGCT ADS6443IRGCR ADS6442IRGCT ADS6442IRGCR TRANSPORT MEDIA, QUANTITY 250, Tape/reel 2000, Tape/reel 250, Tape/reel 2000, Tape/reel 250, Tape/reel 2000, Tape/reel 250, Tape/reel 2000, Tape/reel ADS6445 ADS6444 ADS6443 ADS6442 (1) (2) QFN-64 (2) QFN-64 (2) QFN-64 (2) QFN-64 (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow), θJC = 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB. ABSOLUTE MAXIMUM RATINGS (1) VALUE AVDD LVDD Supply voltage range Supply voltage range Voltage between AGND and DGND Voltage between AVDD to LVDD Voltage applied to external pin, VCM Voltage applied to analog input pins TA TJ Tstg Operating free-air temperature range Operating junction temperature range Storage temperature range Lead temperature 1,6 mm (1/16") from the case for 10 seconds (1) –0.3 to 3.9 –0.3 to 3.9 –0.3 to 0.3 –0.3 to 3.3 –0.3 to 2.0 – 0.3V to minimum ( 3.6, AVDD + 0.3V) –40 to 85 125 –65 to 150 220 UNIT V V V V V V °C °C °C °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback 3 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN SUPPLIES AVDD LVDD Analog supply voltage LVDS Buffer supply voltage Differential input voltage range Input common-mode voltage Voltage applied on VCM in external reference mode CLOCK INPUT ADS6445 Input clock sample rate, Fsrated ADS6444 ADS6443 ADS6442 Sine wave, ac-coupled Input clock amplitude differential (VCLKP– VCLKM) LVPECL, ac-coupled LVDS, ac-coupled LVCMOS, ac-coupled Input Clock duty cycle DIGITAL OUTPUTS CLOAD RLOAD TA Maximum external load capacitance from each output pin to DGND Without internal termination With internal termination –40 5 10 100 85 pF Ω °C 35% 5 5 5 5 0.4 1.5 ± 0.8 ± 0.35 3.3 50% 65% Vpp 125 105 80 65 MSPS 1.45 3.0 3.0 3.3 3.3 2 1.5 ±0.1 1.50 1.55 3.6 3.6 V V Vpp V V NOM MAX UNIT ANALOG INPUTS Differential load resistance (external) between the LVDS output pairs Operating free-air temperature 4 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER RESOLUTION ANALOG INPUT Differential input voltage range Differential input capacitance Analog input bandwidth ADS6445 Analog input common mode current (per input pin of each ADC) ADS6444 ADS6443 ADS6442 REFERENCE VOLTAGES VREFB VREFT ∆VREF VCM Internal reference bottom voltage Internal reference top voltage Internal reference error (VREFT–VREFB) Common mode output voltage VCM output current capability DC ACCURACY No missing codes EO Offset error, across devices and across channels within a device Offset error temperature coefficient, across devices and across channels within a device There are two sources of gain error - internal reference inaccuracy and channel gain error EGREF EGCHAN Gain error due to internal reference inaccuracy alone, (∆VREF /2.0) % Reference gain error temperature coefficient Gain error of channel alone, across devices and across channels within a device (1) Channel gain error temperature coefficient, across devices and across channels within a device DNL INL PSRR Differential nonlinearity, Fin = 50 MHz Integral nonlinearity, Fin = 50 MHz DC power supply rejection ratio ADS6445 ICC Total supply current ADS6444 ADS6443 ADS6442 ADS6445 IAVDD Analog supply current ADS6444 ADS6443 ADS6442 ADS6445 ILVDD LVDS supply current ADS6444 ADS6443 ADS6442 (1) This is specified by design anad characterization; it is not tested in production. Submit Documentation Feedback 5 ADS6445 and ADS6444 ADS6443 and ADS6442 ADS6445 and ADS6444 ADS6443 and ADS6442 –0.9 –0.9 -5 4.5 –1 -0.75 0.1 0.0125 ±0.3 0.005 ±0.6 ±0.5 ±3 ±2 0.5 502 410 360 320 410 322 280 245 92 88 80 75 mA mA mA 2.0 1.8 5 4.5 1 0.75 % FS ∆%/°C % FS ∆%/°C LSB LSB mV/V –15 Assured ±2 0.05 15 mV mV/°C -15 1.0 2.0 ±2 1.5 ±4 15 V V mV V mA 2.0 7 500 155 130 100 81 µA VPP pF MHz MIN TYP 14 MAX UNIT Bits POWER SUPPLY ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature rang