ADC

www.DataSheet4U.com ADS5527 www.ti.com SLWS196 – DECEMBER 2006 12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS FEATURES • • • • • • • • • • • • • • • • • • • • • • • • • • Maximum Sample Rate: 210 MSPS 12-Bit Resolution No Missing Codes Total Power Dissipation 1.23 W Internal Sample and Hold 70.5-dBFS SNR at 70-MHz IF 84-dBc SFDR at 70-MHz IF, 0-dB gain High Analog Bandwith up to 800 MHz Double Data Rate (DDR) LVDS and Parallel CMOS Output Options Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF Reduced Power Modes at Lower Sample Rates Supports Input Clock Amplitude Down to 400 mVPP Clock Duty Cycle Stabilizer No External Reference Decoupling Required Internal and External Reference Support Programmable Output Clock Position to Ease Data Capture 3.3-V Analog and Digital Supply 48-QFN Package (7 mm × 7 mm) DESCRIPTION ADS5527 is a high performance 12-bit, 210-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. With high analog bandwidth and low jitter input clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges. In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. The ADS5527 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode. The device is specified over temperature range (-40°C to 85°C). the industrial ADS5527 PRODUCT FAMILY 210 MSPS 14 bit 12 bit ADS5547 ADS5527 190 MSPS ADS5546 170 MSPS ADS5545 ADS5525 APPLICATIONS Wireless Communications Infrastructure Software Defined Radio Power Amplifier Linearization 802.16d/e Test and Measurement Instrumentation High Definition Video Medical Imaging Radar Systems Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated ADS5527 www.ti.com SLWS196 – DECEMBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. CLKP CLKM DRGND DRVDD AGND AVDD CLOCKGEN CLKOUTP CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M INP SHA INM 12-Bit ADC Digital Encoder and Serializer D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M VCM Reference Control Interface OVR IREF SDATA RESET OE DFS MODE SCLK SEN LVDS MODE PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER ADS5527IRGZT ADS5527 QFN-48 (2) RGZ –40°C to 85°C AZ5527 ADS5527IRGZR (1) (2) TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2500 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 25.41°C/W (0 LFM air flow), θJC = 16.5°C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in PCB. 2 Submit Documentation Feedback ADS5527 www.ti.com SLWS196 – DECEMBER 2006 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE Supply voltage range, AVDD Supply voltage range, DRVDD Voltage between AGND and DRGND Voltage between AVDD to DRVDD Voltage applied to VCM pin (in external reference mode) Voltage applied to analog input pins, INP and INM Voltage applied to input clock pins, CLKP and CLKM TA TJ Tstg (1) Operating free-air temperature range Operating junction temperature range Storage temperature range –0.3 V to 3.9 –0.3 V to 3.9 -0.3 to 0.3 -0.3 to 3.3 -0.3 to 1.8 –0.3 V to minimum (3.6, AVDD + 0.3 V) -0.3 V to AVDD + 0.3 V –40 to 85 125 –65 to 150 UNIT V V V V V V V °C °C °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN SUPPLIES Analog supply voltage, AVDD Digital supply voltage, DRVDD ANALOG INPUTS Differential input voltage range Input common-mode voltage Voltage applied on VCM in external reference mode CLOCK INPUT Input clock sample rate (1) TYP 3.3 3.3 2 1.5 ±0.1 MAX 3.6 3.6 UNIT V V VPP V 3 3 1.45 1.5 1.55 V MSPS DEFAULT SPEED mode LOW SPEED mode Input clock amplitude differential (V(CLKP) - V(CLKM)) Sine wave, ac-coupled LVPECL, ac-coupled LVDS, ac-coupled LVCMOS, single-ended, ac-coupled Input clock duty cycle (See Figure 31) DIGITAL OUTPUTS CL 50 1 0.4 1.5 1.6 0.7 3.3 35% 50% 210 60 MSPS VPP VPP VPP V 65% Maximum external load capacitance from each output pin to DRGND (LVDS and CMOS modes) Without internal termination (default after reset) With 100 Ω internal termination (2) 5 10 100 –40 85 pF pF Ω °C RL Differential load resistance between the LVDS output pairs (LVDS mode) Operating free-air temperature (1) (2) See the section on Low Sampling Frequency Operation for more information. See the section on LVDS Buffer Internal termination for more information. Submit Documentation Feedback 3 ADS5527 www.ti.com SLWS196 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling rate = 210 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0-db gain, DDR LVDS data output (unless otherwise noted) PARAMETER Resolution ANALOG INPUT Differential input voltage range Differential input capacitance Analog input bandwidth Analog input common mode current (per input pin) REFERENCE VOLTAGES V(REFB) V(REFT) VCM Internal reference bottom voltage Internal reference top voltage Common mode output voltage VCM output current capability DC ACCURACY No Missing Codes DNL INL Differential non-linearity Integral non-linearity Offset error Offset temperature coefficient Gain error Gain temperature coefficient PSRR I(AVDD) DC Power supply rejection ratio Analog supply current LVDS mode, IO = 3.5 mA, RL = 100 Ω, CL = 5 pF CMOS mode, FIN = 2.5 MHz, CL = 5 pF LVDS mode LVDS mode In STANDBY mode with clock stopped With input clock stopped POWER SUPPLY 306 66 47 372 1.23 100 100 1.375 150 150 mA mA mA mA W mW mW -0.8 -2 -10 Assured 0.5 1 5 0.002 ±1 0.01 0.6 1.0 2 10 LSB LSB mV ppm/°C %FS ∆%/°C mV/V Internal reference mode Internal reference mode Internal reference mode Internal reference mode 0.5 2.5 1.5 ±4 V V V mA 2 7 800 342 VPP pF MHz µA TEST CONDITIONS MIN TYP 12 MAX UNIT bits I(DRVDD) Digital supply current ICC Total supply current Total power dissipation Standby power Clock stop power 4 Submit Documentation Feedback ADS5527 www.ti.com SLWS196 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling rate = 210 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0-db gain, DDR LVDS data output (unless otherwise noted) PARAMETER AC CHARACTERISTICS FIN = 20 MHz FIN = 70 MHz FIN = 100 MHz FIN = 170 MHz SNR Signal to noise ratio FIN = 230 MHz FIN = 300 MHz FIN = 400 MHz RMS output noise 0 dB gain, 2 VPP FS (1) 3 dB gain, 1.4 VPP FS 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS 68 70.7 70.5 70.3 69.5 69.4 68 68.5 67.4 67.3 66.4 0.35 86 75 84 78 79 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS 67.5 75 78 74 76 68 70 70.5 70.2 69.3 68.0 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS FIN = 300 MHz FIN = 400 MHz FIN = 20 MHz FIN = 70 MHz FIN = 100 MHz FIN = 170 MHz HD2 Second harmonic FIN = 230 MHz 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS FIN = 300 MHz FIN = 400 MHz 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS 75 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS 0 dB gain, 2 VPP FS 3 dB gain, 1.4 VPP FS 67.4 67.1 66.4 66.3 63.5 65.0 91 88 87 87 86 88 78 80 69 71 dBc dBFS dBc LSB dBFS TEST CONDITIONS MIN TYP MAX UNIT Inputs tied to common-mode FIN = 20 MHz FIN = 70 MHz FIN = 100 MHz FIN = 170 MHz SFDR Spurious free dynamic range FIN = 230 MHz FIN = 300